People walk past the headquarters of ChangXin Memory Technologies in Hefei, in China's eastern Anhui province on July 16, 2026. CN-STR/gettyimages.com

China's leading DRAM manufacturer, ChangXin Memory Technologies (CXMT), has produced high-bandwidth memory chips using the HBM3E standard for the first time — in small quantities, and now in the hands of two domestic AI chip designers for qualification testing. The chips have been delivered to Alibaba Group's T-Head semiconductor division and Beijing-based Cambricon Technologies, which are evaluating them alongside their own AI processors ahead of a potential commercial integration as early as 2027 — making this the first time a Chinese company has produced functional HBM3E at any scale. Whether those tests pass is still an open question, and CXMT's yield, specification, and timing challenges are real. But the claim that has appeared in every prior assessment of China's AI memory program — that HBM3E production was a 2027 target — is no longer accurate. It is happening now, in September 2026, one year earlier than projected.

That shift in timeline is the story. Export controls imposed by Washington beginning in October 2022 and tightened specifically to target HBM in December 2024 were designed to maintain a durable capability gap in the one technology that AI accelerators cannot operate without. The gap has not closed — CXMT remains an estimated two to five years behind the leading producers on different measures of technical sophistication — but the controls have not prevented China from crossing the threshold into HBM3E production. They delayed it; they did not stop it.

Why HBM3E Is the Component That Determines Who Can Build Serious AI

High-bandwidth memory works by stacking individual DRAM dies vertically and connecting them through microscopic copper pillars called through-silicon vias (TSVs), then co-packaging the completed stack directly beside the AI processor on a silicon interposer. The result is a memory interface that is 1,024 bits wide in HBM3E — between 16 and 32 times wider than conventional DDR5 DRAM — enabling peak pin speeds of up to 9.6 gigabits per second and a total bandwidth per stack of up to 1.228 terabytes per second (TB/s). Conventional DDR5, by contrast, delivers roughly 50 to 60 gigabytes per second. An AI accelerator operating with conventional DRAM would spend the overwhelming majority of its compute cycles waiting for data; HBM eliminates that bottleneck at the cost of vastly greater manufacturing complexity.

That complexity is precisely what makes HBM a durable competitive moat. Stacking eight or twelve DRAM dies with sub-micron precision, achieving acceptable yield across the full stack, managing thermal stress, die warpage, bonding defects, and maintaining reliable electrical connections through thousands of TSVs — every step amplifies the risk of a defective unit. SemiAnalysis, in its June 2026 CXMT deep-dive, modeled CXMT's HBM3 eight-high stack yield at approximately 35% on the front end and 70% on the back end, producing an overall yield of roughly 25%. That means three of every four CXMT HBM stacks produced at that time failed quality testing — an expensive baseline from which to begin commercial supply. The challenges multiply as stack height increases, and CXMT has limited twelve-high stack experience. HBM3E yield figures for CXMT have not been publicly disclosed, and the company, T-Head, and Cambricon have all declined to confirm the testing program on the record.

What CXMT Has Achieved — and the Two-Year Gap That Remains

Until Monday's report from The Information, CXMT's publicly confirmed HBM activity consisted of HBM3 samples delivered to Huawei for AI accelerator evaluation during the second half of 2025, with no disclosed yield, specification, or timeline data for HBM3E. Every major industry assessment — including those published by Tom's Hardware, SemiAnalysis, and TrendForce — identified HBM3E volume production as a 2027 target, placing CXMT approximately three years behind the commercial leaders.

The new data point narrows one of those claims but not all of them. CXMT has produced HBM3E in small quantities — a stage the industry calls "risk production," meaning the manufacturing process is being validated rather than optimized — and the chips have passed internal quality hurdles sufficient to be placed in customer hands for testing. That is meaningfully different from a sample demonstration or a technology roadmap. It means CXMT has built a TSV stacking process for HBM3E that produces at least some functional units.

What has not changed: SK Hynix entered HBM3E mass production in 2024 — roughly two years before CXMT's initial small-batch run. Both SK Hynix and Samsung have since advanced to HBM4 mass production and have delivered HBM4E customer evaluation samples featuring data-transfer rates of up to 16 gigabits per second per pin. CXMT's HBM3E production puts it one generation behind the current commercial standard, not at parity with it. The three-to-five-year technical gap estimated by people familiar with the company accounts for this multi-layer distance — not just the specific generation that has been produced in risk quantities, but the infrastructure, process maturity, tooling, and supply ecosystem that underpins high-volume production at competitive yield.

Tom's Hardware contributing writer Anton Shilov put the significance precisely: the HBM3E generation itself matters less than CXMT's ability to manufacture usable HBM at all. A company that can produce functional HBM stacks has demonstrated a process capability that can be iterated. A company that cannot has not.

Alibaba T-Head and Cambricon: Why These Two Customers Matter

The selection of Alibaba's T-Head semiconductor unit and Cambricon Technologies as the initial recipients of CXMT's HBM3E chips is not incidental. Both are among the most commercially viable domestic Chinese AI chip designers, and both face a supply-chain constraint that CXMT HBM3E is specifically designed to address.

Cambricon has targeted production of roughly 500,000 AI chips in 2026, but prior analysis by Tom's Hardware identified HBM supply as a primary constraint — AI accelerators require large HBM pools to keep compute units saturated, and HBM3 and HBM3E supply from South Korean producers operates under US export restrictions. Cambricon's customers — cloud operators building AI infrastructure in China — may face delays if chip volume is available but matching HBM modules are not. A qualified domestic HBM source would remove that constraint entirely.

T-Head, Alibaba Group's chip design arm, faces the same structural problem. Alibaba Cloud's AI infrastructure buildout depends on Chinese-designed accelerators that currently have no reliable domestic HBM supplier. Western HBM from SK Hynix, Samsung, and Micron is either subject to export controls or requires individual license review for advanced AI applications. CXMT HBM3E — if it qualifies — would change that picture for Chinese hyperscaler AI development specifically.

Neither Cambricon, T-Head, nor CXMT has confirmed the testing program publicly, and no qualification timeline has been announced. If testing proceeds as reported, products incorporating CXMT's HBM3E could reach commercial availability as early as 2027 — ahead of CXMT's previously stated target for mass production expansion.

How CXMT Makes HBM Without the World's Most Advanced Tools

CXMT's entire manufacturing roadmap runs on deep-ultraviolet (DUV) lithography — older 193nm-wavelength tools that use multi-patterning techniques rather than the extreme-ultraviolet (EUV) systems that Samsung, SK Hynix, and Micron use for leading-edge production. ASML has never shipped an EUV machine to China; Dutch export law prohibits it. CXMT compensates through self-aligned double patterning and self-aligned quadruple patterning (SADP/SAQP), running each circuit layer through multiple exposure passes — a process that accumulates small overlay errors and adds manufacturing steps, raising cost-per-bit versus single-pass EUV production.

For HBM specifically, the equipment constraint is a real but not fully prohibitive factor. HBM manufacturing requires two distinct technical capabilities: the DRAM die lithography (where DUV limitations apply) and the TSV stacking and packaging process (which is less directly dependent on EUV patterning). CXMT's back-end packaging capabilities — developed with domestic OSATs including Tongfu Microelectronics — appear to be more mature than its front-end lithography position would suggest. Micron manufactured its D1α DRAM generation without EUV in 2021, demonstrating that functional HBM production is achievable without the most advanced lithography tools — at a cost-per-bit penalty.

That penalty is real. CXMT's cost per bit on DDR5 runs more than 30% above Samsung, SK Hynix, and Micron. That structural disadvantage is masked at current supercycle DRAM prices but would become decisive in a normalized market — and it applies to HBM production costs as well, where yield losses at scale compound the arithmetic significantly.

SemiAnalysis models CXMT's HBM wafer starts at approximately 30,000 per month in 2026, rising to roughly 55,000 by end-2027, out of a projected total monthly wafer capacity of approximately 350,000 wafer starts by end-2026. Each HBM package requires multiple large DRAM dies, meaning that even modest growth in HBM output consumes a meaningful share of total manufacturing capacity — a tension CXMT must manage carefully as it pursues its 2027 scale-up target.

Financial Firepower Behind the Effort

CXMT enters this qualification race with substantially more resources than at any point in its history. The company's landmark Shanghai STAR Market IPO in July raised ¥57.9B CNY (approximately $8.6B USD) — Asia's largest initial public offering of 2026 — with first-day shares surging 472%. The company's first-half 2026 revenue surged to ¥150.3B CNY (approximately $22.4B USD), a near-tenfold increase year-over-year, with net profit reaching ¥77.6B CNY (approximately $11.5B USD) — a dramatic financial turnaround from prior-year losses.

Of the ¥29.5B CNY (approximately $4.4B USD) in named IPO project funding, ¥13.0B CNY (approximately $1.9B USD) is directed to DRAM technology upgrades, ¥9.0B CNY (approximately $1.3B USD) to next-generation DRAM research, and ¥7.5B CNY (approximately $1.1B USD) to manufacturing line upgrades. Notably, the prospectus contains no dedicated HBM expansion project and no disclosed earmarked HBM capital — a disclosure about priorities that Tom's Hardware flagged at the time of the IPO. The HBM3E small-batch production has evidently proceeded on internal R&D budget rather than a named capital project.

The revenue windfall is structurally enabled by a market condition that may not persist. Samsung, SK Hynix, and Micron redirected manufacturing capacity toward HBM for AI accelerators, effectively vacating portions of the commodity DRAM market — DDR5 and LPDDR5X for PCs, smartphones, and servers. CXMT filled the vacancy. When the incumbents' expanded HBM capacity comes online and they redirect production back to commodity DRAM, CXMT's 30%-plus cost disadvantage becomes a margin problem. The HBM3E qualification program is, in part, an attempt to secure the higher-margin AI memory market before that cyclical reversal arrives.

What the Incumbents Are Doing While CXMT Qualifies

For Samsung, SK Hynix, and Micron, CXMT's HBM3E risk production represents no immediate competitive threat. SK Hynix alone commands more than half of the global HBM market by revenue and is in mass production of HBM4 at 16-layer stacking; Samsung shipped 3.6 TB/s HBM4E samples to major customers on May 29, 2026 — twelfth-generation-stacked chips. Samsung also revealed a roadmap for HBM5 and a more radical zHBM architecture that places memory above the processor rather than beside it, targeting up to eight times the performance of HBM5 at significantly better energy efficiency.

At the same time, Micron's HBM architecture fellow Raghu Sreeramaneni presented at Hot Chips 2026 in Stanford, California on August 23, documenting a structural "memory wall" in which AI chip TFLOPS grow roughly three times as fast as HBM bandwidth — a gap that will widen through at least 2038 even as HBM advances to HBM8. That finding, covered in TechTimes' Hot Chips analysis, means that even HBM3E — which CXMT is only now producing — is already architecturally insufficient for the most demanding AI training workloads, which require HBM4 or HBM4E. Chinese AI chip designers building systems with CXMT HBM3E will be working with memory that is fully capable for many inference and moderate training tasks, but architecturally limited relative to the top-end AI hardware that Western and Korean suppliers are shipping today.

Goldman Sachs, in an August 26, 2026 post-IPO supply model, projected that CXMT will supply half of China's DRAM demand and 40% of its high-bandwidth memory demand by 2028 — a forecast that would represent a dramatic acceleration from CXMT's current HBM position, and one that Goldman framed as China's semiconductor self-sufficiency strategy entering "a full-fledged commercialization phase."

Does CXMT HBM3E Undermine the Export Control Architecture?

The strategic question this production milestone raises is not primarily about CXMT's market share or qualification timeline. It is about whether the export control architecture built around denying China access to advanced HBM has functioned as designed.

The controls were designed to prevent China from acquiring HBM from Western or Korean suppliers, and to prevent CXMT from acquiring the manufacturing equipment — specifically advanced DUV tools restricted in October 2022 and HBM-specific controls added in December 2024 — needed to produce it domestically. Those restrictions succeeded in slowing CXMT's progress and in making HBM production more expensive than it would otherwise be. They have not prevented CXMT from crossing the HBM3E production threshold.

Kyle Chan, a fellow at the Brookings Institution specializing in China technology policy, has characterized CXMT as China's best current shot at eventually developing domestic HBM capability. The risk production milestone confirms that assessment is now more accurate than it was six months ago. The question policy analysts and industry observers will be tracking over the next eighteen months is whether CXMT can close the distance from risk production — small batches, uncertain yield, no public specification — to commercial production at a scale and price point that meaningfully reduces Chinese dependence on foreign HBM supply.

The three-to-five-year technical gap cited by people familiar with the company reflects the full distance from where CXMT is today to where SK Hynix and Samsung are today — not where those companies will be in 2028, when CXMT is targeting meaningful HBM production volume. The incumbents will continue to advance. The race is not against a fixed target.

What Chinese AI Builders Need Before This Matters

The milestone CXMT has achieved is real and the timeline acceleration is real. The qualifications on it are equally real and should not be elided.

CXMT's HBM3E risk production does not mean China has a domestic HBM supply chain. It means China has a company that can produce some functional HBM3E units, which are currently undergoing customer qualification, with no publicly confirmed specification, no disclosed yield metric, no announced production volume, and no confirmed commercial agreement. Qualification testing for a new memory vendor integrating with an existing AI chip platform typically takes six to eighteen months. If T-Head or Cambricon qualifies CXMT HBM3E, the next barrier is whether CXMT can supply it in volume — which requires yield improvement, capacity conversion, and packaging scalability that are separate engineering challenges from achieving initial risk production.

None of that diminishes the strategic significance of the milestone. It does establish that the distance between "CXMT is making risk-production HBM3E" and "China has a domestic HBM supply chain for AI" is still substantial — and that the 2027 commercial integration timeline cited in Monday's report is the optimistic scenario contingent on multiple technical and manufacturing hurdles being cleared in succession.

For AI infrastructure builders, memory procurement planners, and export control policy analysts: the timeline for domestic Chinese HBM has advanced by a year. Whether it has advanced far enough to matter for the AI hardware supply chain before 2028 is the question this qualification program will answer.

Exchange rate as of September 1, 2026; conversions are approximate.

Frequently Asked Questions

What does CXMT's HBM3E production mean for US export controls on AI memory?

Export controls imposed on HBM specifically in December 2024 were designed to maintain a gap in China's AI memory capability. CXMT's HBM3E risk production demonstrates that the controls delayed China's progress — the 2027 volume production target has advanced, in preliminary form, to September 2026 — but did not prevent it. CXMT achieved this milestone using only DUV lithography tools, without EUV access. The controls succeeded in raising CXMT's costs (a 30%-plus cost-per-bit gap versus incumbents) and limiting yield (roughly 25% for HBM3 stacks per SemiAnalysis modeling), but they did not keep CXMT from crossing the functional HBM3E production threshold. Whether commercial-scale domestic HBM production follows by 2027-2028 remains the open question.

How far behind is CXMT compared to SK Hynix and Samsung on HBM?

SK Hynix entered HBM3E mass production in 2024 — roughly two years before CXMT's initial small-batch run. Both SK Hynix and Samsung are already in HBM4 mass production and shipping HBM4E samples with data-transfer speeds of up to 16 Gb/s per pin. People familiar with CXMT describe an estimated three-to-five-year technical gap on overall sophistication, accounting for yield maturity, manufacturing scale, tooling ecosystem, and supply infrastructure — not just the specific generation difference. CXMT producing HBM3E closes neither the single-generation product gap nor the broader technical gap; it demonstrates capability at a production threshold that the incumbents crossed roughly two years ago.

Can AI chip designers use CXMT HBM3E without access to foreign suppliers?

Potentially, but not yet. Alibaba T-Head and Cambricon are currently in qualification testing — a process that typically takes six to eighteen months for a new memory vendor. No qualification has been confirmed, no commercial agreement has been announced, and CXMT has not disclosed yield metrics, specifications, or qualification timelines. If qualification succeeds, Chinese AI chip designers would have a domestic HBM3E option for 2027 products — at a memory generation that is already one behind what Nvidia's current AI platforms require. For inference-focused AI workloads and moderate training tasks, HBM3E is fully functional. For the most demanding AI training, HBM4 is architecturally required.

What does the National Intelligence Law mean for companies receiving CXMT HBM3E samples?

CXMT operates under China's National Intelligence Law (2017), which requires Chinese organizations to cooperate with national intelligence work under Article 7. Article 14 authorizes intelligence agencies to demand that cooperation. For AI chip designers like T-Head and Cambricon testing CXMT HBM3E: the technical specifications, performance requirements, failure modes, and qualification data they provide to CXMT during testing flow through a company subject to these legal obligations. Both T-Head and Cambricon are Chinese companies, so this is not an external security risk for them specifically — but any third-party AI hardware developer or enterprise buyer considering CXMT HBM3E for future products should understand that qualification data shared with CXMT during testing is subject to Chinese government access on demand.