Chen Yanming, the Director of Advanced Packaging R&D at TSMC, elucidated that microchannel cooling technology entails the creation of minuscule fluid channels within the chip or packaging framework. This innovative approach brings the coolant into closer proximity to the heat source, thereby significantly enhancing thermal transfer efficiency. TSMC has already embarked on the integration of this cutting-edge technology and envisions its further development in tandem with advanced packaging architectures.

Chen further disclosed that TSMC's upcoming iteration of CoWoS (Chip-on-Wafer-on-Substrate) technology, poised to debut in 2029, will boast the capability to integrate 24 High Bandwidth Memories (HBMs) within an area that surpasses 14 times the size of a conventional photomask. Over the span from 2024 to 2029, the number of AI computing transistors that can be seamlessly integrated into a single CoWoS package is projected to escalate by more than 48-fold. Concurrently, the HBM bandwidth is anticipated to experience a 34-fold increase, underscoring the imperative for concurrent advancements in cooling technology to keep pace with these remarkable strides.