The market for fan-out panel-level packaging (FO-PLP) and glass substrates is set to grow more than tenfold in five years, as Intel, TSMC, and others race to adopt the large-area packaging that ever-bigger AI chips demand.

Per Counterpoint Research, the global FO-PLP and glass-substrate market will expand from about $650 million in 2024 to more than $8.1 billion in 2030, according to its industry outlook, with FO-PLP for AI and high-performance computing accounting for 45.6% of revenue. Those are projections, not certainties — but the physics behind them is concrete, and it explains why some of the biggest names in chipmaking are pouring in.

Why AI Chips Broke the Wafer

Two physical limits are forcing the change. The first is geometry. Chips are cut from round silicon wafers, but a chip is rectangular, so the bigger the chip, the more wafer area is wasted at the round edges — and AI chips have grown enormous, pushing past the "reticle limit," the maximum area a lithography machine can pattern in a single exposure. Nvidia's Blackwell GPU already spans about 3.3 times the reticle, with next-gen Vera Rubin set to reach around four times. FO-PLP answers the geometry problem by building packages on large rectangular panels instead of round wafers, which wastes far less edge area and fits many more units per run, lifting area utilization to as high as 75% and lowering cost.

The second limit is material. As packages grow large, the substrate beneath them tends to warp when heated during manufacturing, and organic — plastic-based — substrates warp badly enough to hurt yield. Glass solves that because its coefficient of thermal expansion is close to silicon's, so a large glass package stays flat and dimensionally stable where an organic one bends.

Intel and TSMC Lead the Shift

Intel put glass substrates on its advanced-packaging roadmap in 2023 and, at NEPCON Japan in January, showed a sample combining its EMIB 2.5D bridge technology with a glass-core substrate — though it has reportedly moved to license its glass technology rather than mass-produce it itself. TSMC last year unveiled Chip on Panel on Substrate (CoPoS), a 310×310mm panel platform meant to move to glass cores, with a pilot line at subsidiary VisEra this year, trial production in 2027, and volume production targeted for the second half of 2028.

Geographically, Counterpoint expects East Asia — Taiwan, Japan, and China — to hold 84.8% of panel-level packaging capacity by 2030, with Japan growing fastest on glass investment.

A Crowded Global Field

The race extends well beyond the two leaders. Japan's Rapidus is developing 600×600mm glass panel packaging using Lam Research equipment; Ibiden and Taiwan's Innolux are co-developing glass cores with TSMC; China's BOE signed a three-year memorandum with Corning in May and began operating a glass pilot line; and Visionox is expanding glass facilities.

In Korea, SKC's Absolics leads, with a plant in Covington, Georgia, preparing for volume production and sampling to AMD; Samsung Electro-Mechanics is set to finalize a glass-core joint venture with Japan's Sumitomo Chemical Group; LG Innotek is developing glass-substrate processes with UTI; and Samsung Electronics is working on glass interposers. Each is chasing the same prize — qualification from a major AI-chip customer — on timelines that mostly land between 2027 and 2030.

The Hurdle That Decides the Race

For all the investment, one problem still gates the whole shift: the through-glass-via (TGV) process. To carry signals vertically through a glass substrate, manufacturers must drill and align microscopic holes through a brittle material with extreme consistency — and TGV yield remains the hardest unsolved step, where consistency and reliability still limit commercialization. Industry estimates put glass-substrate manufacturing yields well below the levels needed for cost-effective high-volume production, largely because of that brittleness and TGV complexity. Whoever masters it first stands to set the standards, and capture the pricing leverage, for the packaging era that AI has ushered in.

Frequently Asked Questions

What is fan-out panel-level packaging (FO-PLP)?

FO-PLP is an advanced chip-packaging method that builds packages on large rectangular panels instead of round silicon wafers. "Fan-out" means the package's connection points are spread out beyond the chip's own footprint, allowing more input/output pins without enlarging the chip. Using rectangular panels rather than round wafers wastes far less edge area and lets manufacturers process many more units at once — raising area utilization to as high as 75% and lowering cost. That makes FO-PLP well-suited to the very large packages that modern AI and high-performance-computing chips require.

Why are glass substrates used for AI chips?

As AI chip packages grow larger, the substrate they sit on becomes prone to warping during the heat of manufacturing. Traditional organic (plastic-based) substrates warp enough to reduce yield in large packages. Glass has a coefficient of thermal expansion close to that of silicon, so a large glass package stays flat and dimensionally stable under heat. Glass also offers high flatness and good electrical properties, which help with the dense interconnects and signal integrity that large AI processors need — making it a leading candidate to replace organic substrates for the biggest chips.

What is TSMC's CoPoS?

CoPoS, or Chip on Panel on Substrate, is TSMC's panel-level packaging platform, built on a 310×310mm panel format and intended to move toward glass-core substrates. According to industry reporting, TSMC plans a pilot line at its VisEra subsidiary in 2026, trial production in 2027, and volume production in the second half of 2028. The approach replaces the round wafer carrier used in current packaging with a square panel, improving utilization by eliminating the wasted edge and corner area of a round format. These are company targets and can shift as the technology matures.

What is a through-glass via (TGV)?

A through-glass via is a microscopic vertical hole drilled through a glass substrate and filled with conductive material, allowing electrical signals to pass from one side of the glass to the other. TGVs are what make glass usable as a packaging substrate, enabling dense 3D interconnection. But forming them consistently is difficult: glass is brittle, and achieving reliable, high-yield TGVs at scale is widely regarded as the key remaining hurdle to commercializing glass substrates. Progress on TGV yield is one of the clearest signals of how quickly glass-based packaging will arrive.