Samsung Electronics has filed a patent aimed at the reliability problems that crop up as high-bandwidth memory (HBM) stacks grow taller — reworking the "dummy die" that caps the stack to improve yield and stability ahead of the HBM4E and HBM5 era, according to Electronic Times (ETNews).

The patent is a reminder that the HBM race is increasingly won or lost on packaging rather than the memory cells themselves — and that one of the harder problems lives in an unglamorous place: the dead chip that sits on top of the stack and does no computing at all.

What a Dummy Die Does, and Why Height Breaks It

An HBM chip is a tower. Working DRAM dies are stacked on a base die and capped at the very top by a "dummy" die — a piece of silicon that performs no computation but earns its place by bringing the package to the exact height a customer's design requires, protecting the stack mechanically, and helping channel heat out the top.

As towers climb from today's 12 layers toward 16 and beyond, that cap becomes a liability. Different materials in the stack expand by different amounts as they heat and cool, and over a taller tower those mismatches concentrate near the top, warping the dummy die — the industry term is "warpage" — and inviting cracks and delamination, where the layers begin to peel apart. The cost shows up as yield. ETNews reports that yields, which typically fall 10 to 20 percentage points going from 8 to 12 layers, drop more steeply toward the 40–60% range nearing 16 layers — meaning a large share of parts can be lost. As an industry source put it, in high-stack HBM of 12 layers or more, the warpage of the topmost dummy die is a key variable affecting yield.

What the Patent Actually Changes

Samsung's patent, dated June 28, attacks the shape of that cap. Instead of a plain block, it sculpts the dummy die's sides into a three-tiered, stepped-and-curved, inverted-pyramid form — a narrow bonding surface that widens upward, with broken-up, convex side faces — a geometry designed to distribute mechanical stress more evenly and resist warping.

To cut that delicate shape, ETNews reported, the patent uses "deep groove sawing," a laser-based, high-precision dicing process that carves deeper, cleaner grooves than a conventional mechanical blade while minimizing damage to the silicon's crystal structure. Two further details round out the design: pre-formed trenches in a non-bonding region of the die catch sawing debris so it cannot contaminate the critical bond interface, and the bonding insulation layer is tuned to a 1–10 micrometer spacing so that reshaping the die does not choke the heat path — by trimming the molding compound around the protrusions, the patent suggests it may even improve heat flow. In short, it is a fix measured in micrometers of die geometry, meant to let the stack go taller without the cap giving way.

A Forward-Looking Piece of a Bigger Puzzle

The technology is forward-looking, and a patent filing is a research disclosure rather than a shipping product. Samsung is expected to pair it with existing HBM packaging methods — hybrid bonding and its Heat Path Block (HPB) thermal design, which it showcased alongside an HBM5 mockup at Computex in June — to bolster overall reliability and, it hopes, expand its HBM share. The industry source described the patent as a future-oriented technology aimed at 16-layer-plus HBM5 configurations, which Samsung is targeting for around 2028.

That timing matters for the competitive picture. Samsung, SK hynix, and Micron are all racing toward taller, hotter HBM stacks for the next generation of AI accelerators, and each is attacking the same physics from a different angle — SK hynix with its own in-package cooling work, Samsung with a combination of bonding, thermal, and now die-geometry techniques. The dummy-die patent is a small but telling piece of that effort: evidence that getting to the next generation of AI memory is as much a battle over the shape of a single capping chip as over the nanometers inside the memory itself.

Frequently Asked Questions

What is a dummy die in HBM?

A dummy die is a piece of silicon placed at the very top of a high-bandwidth memory (HBM) stack that performs no computing function. Its jobs are structural and thermal: it brings the overall package to the precise height a customer's design requires, protects the stack of working memory dies beneath it from mechanical damage, and helps conduct heat out of the package. Because it sits at the top of an increasingly tall stack, its mechanical reliability becomes more important as HBM adds layers, which is why Samsung's patent focuses on reshaping it.

Why do HBM yields drop with more layers?

Stacking more memory dies introduces more opportunities for defects and more mechanical stress. The different materials in the stack expand and contract by different amounts as they heat and cool, and in a taller stack those mismatches concentrate and can warp or crack the dies, especially the cap at the top. According to ETNews, yields typically fall 10 to 20 percentage points moving from an 8-layer to a 12-layer stack, and drop more sharply toward the 40–60% range approaching 16 layers. Improving the reliability of the topmost dummy die is one way to limit that yield loss.

What is deep groove sawing?

Deep groove sawing is a high-precision method for cutting semiconductor wafers into individual chips. According to ETNews, the process described in Samsung's patent is laser-based and cuts deeper, cleaner grooves than conventional blade sawing — the mechanical method that uses a spinning blade — while minimizing damage to the silicon's crystal structure. That precision lets Samsung shape the dummy die's edges into the complex stepped-and-curved form the patent describes, which would be difficult to achieve with a standard blade.

When is HBM5 coming?

HBM5 is the generation of high-bandwidth memory after HBM4 and HBM4E, designed for taller stacks, higher data rates, and greater capacity for AI accelerators. Samsung showcased an HBM5 mockup, along with its Heat Path Block thermal design, at Computex in June 2026, and the industry source cited by ETNews describes the dummy-die patent as aimed at 16-layer-plus HBM5 configurations targeted for around 2028. Exact timing depends on how quickly the underlying packaging, thermal, and yield challenges are solved, and industry estimates for HBM5 production vary.