On October 20th, Liu Jiuyang, a doctoral candidate in Zou Xuecheng's team at the School of Integrated Circuits, achieved a notable milestone in the architectural realm through his research endeavor, "High-Performance RISC-V Vector Core." His study was accepted for presentation at the 58th International Symposium on Microarchitecture (MICRO), a premier conference in the field of computer architecture, where he was also invited to share his research insights. The research unveils an open-source, high-performance RISC-V vector core dubbed "Titan-I," which incorporates out-of-order execution capabilities. This innovation effectively tackles the scalability issues faced by vector processors in contemporary computing, providing a fresh approach for domains demanding high computational power, such as high-performance computing (HPC) and cryptography. The title of the paper is "Titan-I: An Open-Source, High-Performance RISC-V Vector Core."