Samsung Foundry plans to tape out its Physical AI chiplet platform with design partner Cadence Design Systems in early 2027, with volume production of commercial chips targeted for the second half of that year — a move that signals a structural shift in how Samsung sells foundry services to the robotics, automotive, and industrial automation markets.

According to industry sources cited by ETNews, Samsung has locked in a production timeline and a go-to-market strategy for the platform. Tape-out marks the point at which a chip design is finalized and handed off to manufacturing; volume production at this scale typically follows six months later.

The timing is significant. Samsung Foundry holds roughly 7 percent of the global foundry market — a distant second to TSMC's near-70-percent dominance — and has spent years rebuilding customer confidence after yield problems at its 3nm process node. The Physical AI chiplet platform represents a deliberate effort to open a new lane: selling a single pre-engineered chip architecture to dozens of smaller customers simultaneously, rather than building bespoke silicon for each one.

Platform Model Inverts Samsung Foundry's Traditional Business

Samsung's foundry division has historically operated on a bespoke model: one fabless customer, one custom chip design, one manufacturing contract. Each chip is engineered from scratch to that customer's exact specifications, which means high upfront non-recurring engineering costs and long design cycles — barriers that keep most Physical AI startups out of advanced silicon entirely.

The chiplet platform inverts that model. Samsung and Cadence have pre-built roughly 60 to 80 percent of the core functionality that Physical AI workloads typically require — a central processing unit, a neural processing unit for AI inference, a memory interface, and PCIe connectivity — into a validated base chip on Samsung's SF5A 5-nanometer process node. A customer needing a chip for an autonomous vehicle, a factory robot, or a drone takes that base, adds the remaining 20 to 40 percent of custom functionality their use case requires, and tapes out a finished chip — without designing one from scratch.

The chiplet architecture makes that customization practical. Rather than integrating everything into a single monolithic die, the platform links multiple semiconductor dies — chiplets — in a single package using Universal Chiplet Interconnect Express die-to-die connectivity. Customers can slot in additional chiplets to add specific capabilities: higher compute density for a more sophisticated autonomy stack, additional sensor interfaces for industrial equipment, or specialized radar processing for advanced driver-assistance systems.

What Physical AI Chips Actually Process

Physical AI refers to the class of AI systems that must perceive, reason, and act in the real world in real time — not in a data center, but on the device itself. A robot navigating a warehouse floor, a car identifying a pedestrian mid-turn, and a factory camera flagging a defective part are all Physical AI workloads. Each requires real-time sensor fusion, vision processing, and deterministic low-latency control that data-center-class processors are not optimized to deliver.

Traditional system-on-chip designs — where all functions are integrated into a single piece of silicon — are hitting fundamental manufacturing limits: routing density, thermal budgets, and the maximum area a single die can occupy within a lithography machine's exposure field. The chiplet approach breaks those limits by splitting functions across multiple dies that are then packaged together, allowing designers to mix and match the best process technology for each component.

Cadence's Spec-to-Packaged-Parts ecosystem, announced in January 2026, supplies the pre-verified intellectual property that populates Samsung's base chip: initial IP partners include Arm, Arteris, eMemory, M31 Technology, Silicon Creations, and Trilinear Technologies, with silicon analytics handled by proteanTecs. Arm's Zena Compute Subsystem — a pre-integrated processor and system IP package designed specifically for automotive and robotics applications — forms part of the core architecture.

How Does Samsung's Chiplet Platform Target Robotics Chip Startups?

The platform's explicit target customer is the Physical AI startup that needs competitive silicon but cannot justify the cost of a clean-sheet chip design. A robotics company building warehouse automation systems, for example, would previously have faced years of design work and hundreds of millions of dollars in engineering costs to get a custom chip to tape-out. With Samsung's platform, it takes the pre-verified base, specifies the differentiated features its robots require, and tapes out on a process node where Samsung has accumulated significant manufacturing experience.

Samsung's SF5A node carries automotive-grade process qualifications: it is AEC-Q100 aware — the automotive industry's reliability standard — and includes design-for-test flows and zero-defects-per-million practices required for safety-critical systems. That matters for Physical AI applications, where a chip failure in an autonomous vehicle or a surgical robot has consequences that a data center chip failure does not.

An earlier silicon validation of Cadence's base system chiplet — integrating the chiplet framework, UCIe 32G connectivity, and LPDDR5X memory interface — was completed before the partnership's public announcement, meaning the core architecture has already been confirmed to work in silicon.

Samsung Foundry's Execution Record Matters Here

Whether Samsung can deliver this platform to commercial customers on schedule is a legitimate question. The company's foundry division has posted losses for multiple consecutive years, and its 3nm process suffered from reported yields as low as 10 to 30 percent during early production — far below the roughly 60 percent threshold the industry considers sufficient for mass manufacturing profitability. Customers including Qualcomm and Nvidia redirected advanced-node orders to TSMC during that period.

The situation has improved. Samsung's foundry utilization exceeded 80 percent in the first quarter of 2026, its highest level in over a year. Its SF2P 2-nanometer process has reportedly reached yields near 70 percent, and the Tesla AI6 automotive chip contract — a confirmed $16.5 billion multi-year deal — has restored external confidence in Samsung's advanced manufacturing roadmap.

The Physical AI chiplet platform targets the SF5A node, not Samsung's newest 2nm processes, which means it benefits from a more mature yield profile. That is a deliberate design choice: Physical AI startups need predictable manufacturing costs and supply, not cutting-edge transistor density.

Supply chain analyst Ming-Chi Kuo at TF International Securities has previously warned that Samsung's ability to secure high-end orders depends on sustained yield improvement and the risk that deeper TSMC-U.S. government cooperation could narrow Samsung's competitive window. The Physical AI platform, by targeting a different customer segment — startups rather than hyperscalers — partially sidesteps that competitive dynamic.

Frequently Asked Questions

When will Samsung's Physical AI chiplet platform be available?

Samsung is targeting tape-out — the point at which the chip design is finalized and sent to manufacturing — in early 2027, according to ETNews. Volume production of commercial chips is expected in the second half of 2027, following the six-month manufacturing cycle that typically separates tape-out from mass production.

How does the Samsung Cadence chiplet platform work for robotics and automotive chip design?

The platform provides a pre-verified base chip built on Samsung's 5nm SF5A process, covering roughly 60 to 80 percent of the core functions Physical AI chips require — including a CPU, a neural processing unit, a memory interface, and PCIe connectivity. Customers add the remaining customization for their specific application through additional chiplets slotted into the same package, which means a robotics startup can get a finished chip without a full clean-sheet design cycle.

What is the difference between a chiplet platform and a custom chip?

A custom chip requires a design team to engineer every component from scratch for a single customer's specifications — a process that can take years and cost hundreds of millions of dollars in engineering fees. A chiplet platform pre-builds the commonly needed components into a validated starting point, and customers customize only the remaining portion. This dramatically lowers the barrier to entry for companies that need specialized silicon but lack the resources for a full custom design.

Why does Samsung Foundry's yield rate matter for this platform?

Yield rate — the percentage of chips on a wafer that pass quality tests — directly determines manufacturing cost and supply reliability. Samsung's earlier 3nm process experienced yields as low as 10 to 30 percent at certain stages, which made those chips expensive and discouraged customers. The Physical AI platform targets the SF5A 5nm node, where Samsung's manufacturing experience is more mature, offering customers more predictable costs and supply compared to Samsung's newest process nodes.