At the Long Beach Convention Center, a new category of tool is selling itself with production numbers instead of demo reels — and the semiconductor design world's most important annual gathering is the stage where that distinction is being tested.

The 63rd Design Automation Conference — known in the field as DAC, now officially branded "The Chips to Systems Conference" — opened Sunday evening, July 26, at the Long Beach Convention Center, marking the first time in the conference's six-decade history that it has come to this California coastal city. The conference runs through Wednesday, July 29. This is Day 2.

This morning, Nobel laureate John Martinis, CTO and co-founder of quantum computing startup Qolab, delivered the first keynote of the week in the Grand Ballroom. His session — titled "From Fundamental Science to Building a Superconducting Quantum Computer" — drew on four decades of experimental physics to argue that the path forward for quantum hardware runs directly through the mature semiconductor fabrication practices this audience has spent careers building. Martinis shared the 2025 Nobel Prize in Physics with John Clarke and Michel Devoret for pioneering experiments demonstrating macroscopic quantum mechanical tunneling and energy quantization in superconducting electrical circuits — the foundational work that underlies every superconducting qubit being built today.

The conference has drawn record participation this year. Research Track submissions grew 26.34% year-over-year; the Engineering Track saw 26% comparable growth. More than 55% of the technical program is dedicated to AI and design topics. More than 120 exhibitors — including 15 AI-native companies attending DAC for the first time — are on the show floor this week.

AI-Native EDA Arrives With Numbers

The central argument being stress-tested at DAC 2026 is whether AI in chip design has crossed from demonstration into production. For the first time at this conference, several startups are arriving not with capabilities to show but with metrics to defend.

Bronco AI, exhibiting at Booth 935, is set to unveil its production-grade benchmark for design verification AI on Tuesday. The company's co-founder and CTO Jeffrey Z. Pan is scheduled to present Tuesday at 11:15 AM ET, drawing on production design verification deployments from block-level to full-chip SoC. His session's central claim: an agentic architecture that autonomously produces root-cause analyses and suggested fixes in under 15 minutes, with a 70% end-to-end first-pass debug success rate. Design verification typically consumes more than 70% of chip project effort — a bottleneck the field has struggled to automate for decades.

ChipAgents.ai is reporting a PCIe root-cause analysis and patch completed in roughly 10 minutes — a task that typically requires four to eight hours of human engineering effort. Verkor.io's Design Conductor platform, noted by IEEE Spectrum, constructed a Linux-capable RISC-V core in 12 hours using its AI agent system.

Whether those numbers reflect the whole story is precisely what is being debated here. Simon Davidmann — co-creator of SystemVerilog, founder of Imperas, and a figure whose career encompasses six EDA companies — has framed the central tension in what industry observers are calling "Davidmann's Test": does an AI tool change what a team can verify, or merely how fast they run what they already verify? By that measure, he argues, today's agentic EDA is largely a band-aid on legacy workflows, not yet a rethinking of the underlying toolchain. Davidmann is scheduled to appear on stage twice this week, including at a Wednesday Exhibitor Forum panel focused on AI for SoC verification.

What Actually Happened Sunday Night and Monday Morning

Timothy Costa, General Manager and Vice President of Computational Engineering at NVIDIA, delivered Sunday evening's opening address — a SKYTalk titled "AI Supercomputing Meets EDA: Accelerating the Future of Chip and System Design." His argument: AI supercomputing and EDA are ceasing to operate as separate disciplines, with foundation models and intelligent design flows beginning to transform the chip development pipeline from architecture exploration through verification and deployment.

Sunday's full-day workshops set the intellectual agenda. The Workshop on Chiplet-based Heterogeneous Integration and Co-design tackled the growing ecosystem around 2.5D and 3D packaging and chiplet IP architectures. The In-Memory Architectures and Computing Applications Workshop examined SRAM, DRAM, RRAM, PCM, MRAM, and FeFET technologies as alternatives to traditional von Neumann memory design. The GREAT Workshop — focused on generative-AI red-teaming of hardware trust and assurance — invited teams to use AI to probe hardware Trojans, IP redaction, and autonomous hardware hacking scenarios, surfacing the security risks that emerge when AI enters chip design flows.

This morning, after Martinis's keynote, Griffin Securities Managing Director Jay Vleeschhouwer opened the DAC Pavilion with an analyst session on EDA financial performance through 2025, updated projections through the end of 2026, and the evolution of Cadence and Synopsys market valuations.

Still Ahead Today: The Sessions That Will Define the Week's Narrative

Beginning at 11:15 AM ET, Siemens EDA and NVIDIA will share the stage for a TechTalk titled "From Tools to Agents: Realizing Fully Autonomous EDA Workflows." Amit Gupta, Siemens EDA's Senior Vice President of EDA AI and Custom IC, will join Da Yang, NVIDIA's Senior Director of Product for Semiconductor and EDA, to demonstrate the Fuse EDA AI System and its companion Fuse Agent. The platform is designed to operate autonomously across the complete design flow — from C-to-RTL-to-GDS pipelines through analog and mixed-signal workflows through physical verification and DRC remediation — using what Siemens describes as a "data flywheel" approach for continuous agent refinement.

At 12:15 PM ET, Intel's Lalitha Immaneni, Vice President of Semiconductor Research and Development, will deliver a SKYTalk on heterogeneous integration as the engine of AI performance. Immaneni is expected to describe Intel's System Technology Co-Optimization approach and note that AI and HPC performance demands grew nearly ten times over the two years from 2021 to 2022, a pace that Moore's Law alone cannot sustain. The afternoon brings a security panel focused on building protection into silicon from early RTL stages, followed at 3:00 PM ET by John Cooley of Deepchip's annual Troublemaker Panel — an unscripted debate featuring senior executives from Synopsys, Cadence, Siemens, and other EDA players. The day's DAC Pavilion program closes at 4:00 PM ET with "Agentic AI in EDA: Who's in Control?" — a panel examining governance and responsibility when AI agents make autonomous design decisions.

Tuesday: Qualcomm's CTO, a New Benchmark, and the ROI Question

Tuesday's keynote at 9:00 AM ET belongs to Dr. Baaziz Achour, Executive Vice President and CTO of Qualcomm Technologies. Achour, who has 24 US patents in communications and led Qualcomm's accelerated rollout of 5G, is scheduled to address the design complexity challenge across the full span of AI hardware — from sub-5-watt battery-powered devices to 500-watt cloud servers. His ask of the EDA community: tools that automate SoC assembly across that spectrum, with 3D IC floorplanning, chiplet-aware package design, and thermal co-design as three areas where he argues current EDA capability falls short.

The IEEE CEDA Luncheon Keynote will feature Columbia University's Luca Carloni on the role of open-source hardware in AI for EDA. Carloni's argument, per his published work, is that hardware design data is largely proprietary — creating a structural barrier to training AI models at scale — and that open-source hardware platforms may provide the shared artifacts needed for genuine agentic AI workflows. This is one of the few DAC sessions that confronts the training-data scarcity problem directly: there is no internet-scale corpus of chip design data, which means the teams with proprietary design archives hold the deepest advantage in building AI-native EDA systems.

SemiAnalysis founder Dylan Patel will present at 10:15 AM ET, walking through the data path of a modern AI accelerator from tensor cores through floor plans and transistor structures. Patel's team operates the STEEL analytical lab, which uses field-emission SEM, X-ray tomography, and aberration-corrected STEM to examine the physical structure of as-built AI chips and link micro-architectural topology to real implementation.

Jeffrey Z. Pan of Bronco AI takes the main stage at 11:15 AM ET to formally introduce the company's AI-native verification benchmark. Tuesday's 4:00 PM ET panel — "Is EDA AI Delivering on Its ROI Promise?" — featuring representatives from Microsoft, ARM, Broadcom, and NVIDIA, is expected to examine whether the productivity gains promised by AI in EDA are materializing in production chip teams, or whether the gap between marketing and engineering reality remains wide.

Wednesday: Microsoft and Brain-Machine Interfaces

Wednesday's morning keynote at 9:00 AM ET will come from Jan M. Rabaey, Professor Emeritus at UC Berkeley, on the convergence of CRISPR-based genetic engineering, AI, and brain-machine interfaces — systems that translate neural signals into actionable commands for external devices. Rabaey is receiving recognition at the conference this week for his career contributions to solid-state circuits design.

At 10:15 AM ET, Microsoft Corporate Vice President Artour Levin — who leads AI Silicon Engineering and spent much of his career at Intel — will address the design challenges of building Maia-class custom AI accelerators for Microsoft's hyperscale cloud infrastructure, with a focus on where traditional EDA methodologies break down at accelerator scale: advanced process nodes, large-scale parallelism, and system-level data movement.

Google's Sathya Narasimhan is scheduled to present in Wednesday's Exhibitor Forum on taping out data center silicon on a workload-optimized, agent-driven EDA stack — a production account from a team that designs its own chips using AI-augmented EDA workflows. Verkor.io will describe the 80-hour construction of a TurboQuant LLM inference accelerator using its Design Conductor 2.0 platform. The Engineering Award Ceremony closes the DAC Pavilion program at 3:00 PM ET.

What the Floor Debate Comes Down To

Frank Schirrmeister, DAC Engineering Track program chair and Executive Director at Synopsys, mapped the DAC 2026 AI landscape in a pre-conference analysis: roughly 130 total vendors contributing to floor and engineering sessions, organized into layers from compute infrastructure and model foundations up through agentic AI flows and developer use cases. His map identifies eight companies focused on security across the stack and notes that standards interoperability — specifically the question of whether agent-to-tool interfaces will be standardized or inherited from general-purpose protocols — is the least-settled debate on the show floor.

The deepest structural argument this week is not about which AI model is best or which agentic startup has the best demo. It is about data. Every AI-native EDA claim depends on what chip design data a company can train on. There is no publicly available, internet-scale corpus of semiconductor design data the way there is for language or images. The teams with decades of proprietary design runs, verification outcomes, and layout data — the hyperscalers and large IDMs quietly building their own AI stacks — hold an architectural advantage that no off-the-shelf model can easily replicate. The training data bottleneck is the structural question that Carloni's open-source hardware session will surface Tuesday, that Google and NVIDIA's private EDA programs exemplify, and that the startups in the middle of the stack will eventually have to answer.

DAC 2026 is the first conference where that question is being asked at production scale, with actual silicon and actual benchmarks, rather than as a theoretical provocation. Whether the answer emerges this week or in the years ahead, it is the right question.

On the Exhibit Floor

The exhibition, open today and Tuesday from 10:00 AM to 6:00 PM ET, and Wednesday from 10:00 AM to 4:00 PM ET, in Exhibit Halls A and B, presents a market in visible transition. The three dominant EDA incumbents — Cadence, Synopsys, and Siemens — share floor space with a generation of AI-native startups: Bronco AI, ChipAgents.ai, Normal Computing, Verkor.io, Silimate, Hu-mind, MooresLabAI, Visibl Semiconductors, Architect Labs, and others. The 15 first-time AI-focused exhibitors include companies that did not exist as recognizable entities at DAC two years ago.

The Poster Gladiator competition — running today and Tuesday on the exhibit floor — adds a competitive format to the traditional poster session, with engineering teams defending their work in front of live judges and audiences.

Awards: Honors Presented and This Week's Recognition

Jensen Huang, founder and CEO of NVIDIA, was formally presented with the 2026 IEEE Medal of Honor — the organization's highest technical recognition, accompanied by a $2 million prize — at the IEEE Honors Ceremony in New York City on April 24, 2026. The award recognized his leadership in the development of graphics processing units and their application to scientific computing and artificial intelligence. Huang donated the full prize and a matching contribution from the Jen-Hsun and Lori Huang Foundation to fund graduate engineering scholarships and IEEE TryEngineering STEM programs. The IEEE Medal is being celebrated this week in the DAC awards program.

The 2025 Phil Kaufman Award for Distinguished Contributions to Electronic Systems Design — which was presented to Intel CEO Lip-Bu Tan at a ceremony in San Jose, California, in November 2025 — is being recognized in the DAC 2026 program. The SIGDA Pioneering Achievement Award and the DAC Engineering Award Ceremony will close out the conference's recognition activities at 3:00 PM ET on Wednesday.

DAC 2026 continues through Wednesday, July 29, at the Long Beach Convention Center, Long Beach, California.

Frequently Asked Questions

What is DAC 2026, and why does it matter this year?

The Design Automation Conference, now in its 63rd year and branded "The Chips to Systems Conference," is the primary annual gathering for the global electronic design automation industry — the professionals who build the software tools used to design semiconductor chips. It matters more than usual in 2026 because, for the first time, several AI-native startups are arriving not with demonstrations but with production metrics: debug time cut from hours to minutes, autonomous design flows handling full C-to-RTL-to-GDS pipelines, and new benchmarks specifically designed to measure AI performance in verification. That shift from demo-mode to production-mode is being tested and debated in real time at this conference.

How does agentic AI actually work in chip design, and where is it in the design flow?

A modern chip design flow moves from a high-level description in C or C++ through high-level synthesis (HLS) to register-transfer level (RTL) description, then through logic synthesis, place and route, and physical verification, ultimately producing a GDSII mask file ready for fabrication. Agentic AI is being deployed at multiple stages: some systems use large language models to generate RTL from specifications, others deploy reinforcement learning agents for physical placement, and the most ambitious — like Siemens EDA's Fuse Agent — are designed to operate autonomously across the complete flow, including C-to-RTL-to-GDS, analog/mixed-signal verification, and design rule check remediation. The bottleneck the field is working around is that analog circuits still largely require specialist human design intuition that no model has reliably captured.

Who actually controls the AI-native chip design future — the big EDA companies, the startups, or the chip companies themselves?

This is the central unresolved question at DAC 2026. The incumbent EDA companies (Cadence, Synopsys, Siemens) hold signoff trust and platform gravity built over 40 years — every chip that gets manufactured runs through their tools. The AI startups are closing specific workflow gaps with measurable production results. But the companies with the deepest long-term advantage may be the chip designers themselves: hyperscalers like Google and NVIDIA are quietly building their own AI EDA stacks trained on decades of proprietary design data. Because there is no publicly available, internet-scale corpus of chip design data, the team with the most design history has the model advantage. Open-source hardware initiatives — the subject of Tuesday's CEDA Luncheon Keynote — represent one path to shifting that balance.

What did John Martinis's Nobel Prize win recognize, and why is he speaking at a chip design conference?

The 2025 Nobel Prize in Physics, shared by Martinis with John Clarke and Michel Devoret, recognized experiments from the 1980s demonstrating that a superconducting electrical circuit could behave as a single quantum entity — exhibiting quantum mechanical effects like tunneling through energy barriers and discrete energy levels. That foundational work, carried out using circuits with Josephson junctions, established the basis for modern superconducting qubits. Martinis's presence at DAC reflects his current argument that quantum computing's path to practical scale runs through importing the mature semiconductor fabrication discipline this audience knows — not through new physics, but through better manufacturing of higher-quality qubits.