Huawei’s Director He Tingbo has published a new paper, addressing external concerns about the thermal management challenges associated with 3D-stacked chips through empirical data from the Kirin 2026 chip. This marks her third academic contribution to Tao’s Law, signifying a pivotal transition from theoretical validation to engineering implementation.

The Kirin 2026 chip, leveraging architectural innovation within the same process node, demonstrates significant improvements in power efficiency, area utilization, transistor density, and CPU clock speed. Its folded architecture design shortens signal transmission paths and optimizes interconnect routing, resulting in reduced power consumption and high integration at the 40nm process.

Huawei also revealed its R&D roadmap for the next-generation Kirin 2027 chip, which will further enhance interconnection precision. This advancement opens up new market opportunities for suppliers of related equipment, technologies, and materials.

However, the industrialization of this technology faces three major bottlenecks: EDA (Electronic Design Automation) tools, operating system scheduling optimization, and standardized testing protocols. Enterprises across the industrial chain have responded proactively.

Experts note that the technology is still in the phase of fostering industry-wide consensus and recommend adopting a strategy of "small-scale pilot projects + ecosystem refinement." The timeline for implementation will vary across different fields, with energy efficiency emerging as a key competitive differentiator. The pace at which supporting components evolve will ultimately determine whether this technology can reshape the semiconductor industry landscape.