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On July 27, Samsung Electronics revealed that its upcoming HBM5 memory will leverage a 2-nanometer process featuring a Gate-All-Around (GAA) architecture. This advancement is projected to enhance operating speeds by more than 50% relative to HBM4E, while also facilitating greater integration through Through-Silicon Via (TSV) technology. Drawing upon its expertise with 4-nanometer HBM4 base chips, Samsung is set to expedite the introduction of the 2-nanometer process in HBM5. Furthermore, the company will intensify its collaborative efforts with customers across diverse sectors, including mobile technology, artificial intelligence (AI), High-Performance Computing (HPC), automotive electronics, and robotics, to propel the growth of the semiconductor ecosystem.
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