On July 8, reports surfaced indicating that Intel had recently made public a patent application, shedding light on its progress in developing a cutting-edge high-bandwidth memory architecture known as XBM (Extended Bandwidth Memory). This novel architecture is engineered to serve as a potential replacement for HBM4, achieving this by eliminating the need for a silicon interposer. Instead, it leverages UCIe interconnects and integrates built-in redundancy repair mechanisms. These features are aimed at slashing the costs associated with advanced packaging and mitigating the 'memory wall' bottleneck that hampers AI chip performance.

XBM adopts a back-end-of-line transistor (BEOL) DRAM stacking design. This approach allows it to maintain a package size comparable to that of HBM4, while simultaneously boosting scalability and facilitating defect repair to enhance production yield. The crux of XBM’s innovation lies in its reimagining of the chip’s foundational architecture. It achieves this by relocating the 1T1C memory cells to the back-end-of-line process, positioning them within the metal via stacking area situated atop the transistors, and employing a thin-film transistor process.

Furthermore, Intel has introduced Memory on Package (MoP) and reverse overhang structures to fine-tune the Z-axis stacking height. This optimization results in a more compact, cost-effective packaging solution. XBM is anticipated to enter the commercial market post-2030.