ZEISS Semiconductor Manufacturing Technology opened its first global Semiconductor Innovation Center in Yongin, South Korea on July 9, planting its tool-development operation beside the two fabs that supply more than half the world's high-bandwidth memory — the chip type powering every major AI accelerator on the planet. The 350-square-meter cleanroom, situated inside SurplusGLOBAL's Yongin Semiconductor Equipment Cluster, began hosting collaborative engineering work with Samsung Electronics and SK hynix from day one, with three ZEISS tools already on the floor.

The strategic logic is more consequential than it first appears. ZEISS is not simply opening a sales office. It is relocating a core slice of its tool-development cycle — the step where engineers from equipment suppliers and chipmakers work in the same room to tune instruments against real production samples — to the geography where the world's most critical AI chips are currently being made. ZEISS's optical systems sit inside every ASML EUV lithography scanner ever built; those scanners, in turn, are used to manufacture the overwhelming majority of the world's advanced microchips. Moving tool development adjacent to the Korean fabs is, in structural terms, moving it adjacent to the constraint that determines how fast AI hardware production can scale.

Korea's AI Chip Buildout Made ZEISS's Move Inevitable

South Korea's semiconductor investment posture in 2026 has been unlike anything the industry has seen. In June, President Lee Jae Myung announced a national mega-project framework anchored by commitments from Samsung Group and SK hynix totaling hundreds of trillions of won across new memory fabs, advanced packaging facilities, and AI data center infrastructure.

For ZEISS, the most operationally significant piece of that framework is what it does to timelines. SK hynix's Yongin Semiconductor Cluster, whose four fabrication plants were originally projected for completion in 2045, has now been accelerated to a 2033 target — a 12-year pull-forward. The first fab at the cluster is scheduled to begin operations in 2027, and SK hynix's July 10 Nasdaq debut allocated the majority of its record-setting $26.5 billion raise to that fab and to ASML EUV equipment. Samsung, meanwhile, is simultaneously advancing construction of P5 Fab 1 and P5 Fab 2 — the final phase of its Pyeongtaek campus.

At that pace of capital deployment, the feedback loop between equipment suppliers and fabs — prototype testing, parameter tuning, yield data collection, tool qualification — has to compress. The previous model, in which Korean engineers shipped wafers to ZEISS facilities in Germany, the United States, or Israel and waited for results across time zones and customs delays, is no longer compatible with what the Korean semiconductor industry is trying to accomplish. "The Korean customers wanted access to German technology at the speed of Korea," said Matthew Wilson, VP of the Semiconductor Business Unit at ZEISS Korea, speaking at a media briefing held at the Westin Josun Seoul on July 10.

ZEISS already had meaningful infrastructure in Korea — offices in Seoul, Dongtan, and Pyeongtaek, and more than 100 SMT engineers on the ground — but the Yongin center is a different category of commitment. It is a cleanroom capable of hosting up to four tools simultaneously, designed to run engineering evaluations on customer wafers without them ever leaving the country.

What the NLX-100 Actually Does, and Why the Dose Problem Matters

The first tool on the floor is the ZEISS NLX-100, a 3D X-ray metrology and inspection platform for 300mm wafers. To understand why it exists, it helps to understand what advanced packaging is doing to chip inspection.

In conventional planar chip manufacturing, inspecting a finished die means examining a surface — looking for particles, line edge roughness, pattern defects. When multiple dies are stacked vertically, as they are in HBM, the critical defects are no longer on any surface you can see. They are inside the stack: micro-bumps that didn't fully bond, through-silicon vias that are slightly misaligned, voids in the copper interconnect layer. The only non-destructive way to image those internal structures is with X-rays.

The NLX-100 uses a technique called laminography. Unlike standard computed tomography, which rotates the sample perpendicular to the beam — impractical for a flat, 300mm wafer — laminography tilts the rotation axis to allow volumetric reconstruction of extended flat objects. Thousands of X-ray projections are taken at different angles and computationally assembled into a 3D model using ZEISS's own AI-powered ZEISS INSPECT analysis software. The system was designed end-to-end by ZEISS, from the X-ray source to the analysis software, which gives the company precise control over the tradeoff that defines the tool's usefulness at advanced nodes.

That tradeoff is dose. As hybrid copper bonding pushes feature dimensions toward the single-micron range — copper pads bonded directly to copper pads, without solder bumps — the X-ray resolution required to see the bond quality increases. Higher resolution requires more radiation exposure. Higher radiation exposure risks damaging the very chip being inspected. According to the ZEISS Semiconductor Korea Innovation Center press briefing, Michael Hentschel, Head of Advanced Packaging at ZEISS SMT, explained: "As processes become finer, such as hybrid copper bonding, X-ray resolution must increase, but higher radiation doses can damage chips. From the initial design stage, ZEISS engineered the system to precisely control radiation exposure to address that challenge."

The result is a tool that can non-destructively image micro-bump and TSV structures inside a completed HBM stack without requiring the sample to be cut. That matters because cutting a sample to verify bond quality gives you yield data on chips you have destroyed. Non-destructive inspection gives you the same data while keeping the wafer alive.

DUNE 100: Chemical-Free Wafer Flattening, No Competitors

The second system addresses a different failure mode: wafer warpage. As each successive stacking layer is added to an HBM die — today's HBM3E uses twelve DRAM dies stacked vertically — differential thermal expansion between materials, stress from bonding adhesives, and coefficient-of-thermal-expansion mismatch between the DRAM layers and the base logic die induce bow and warp across the 300mm wafer. A warped wafer during the next process step — lithography, bonding, or dicing — means misaligned features and degraded yields.

The conventional remedy is chemical-mechanical polishing, which grinds the wafer surface with a slurry until it is flat again. CMP is a bulk process: it averages out height variation across the wafer, but it cannot precisely target a localized stress pattern on a specific die region without removing material from adjacent areas that were already flat. It also introduces a new contamination vector via the slurry chemistry.

The ZEISS DUNE 100 corrects wafer warpage without chemicals. It measures the wafer's shape in high precision and then applies a corrective stress pattern — using localized processing on the wafer surface — that counteracts the existing deformation. This can address both global wafer bow and local distortion within selected die regions in a single step. Karoline Pigdon, Head of Semiconductor Fab Solutions at ZEISS, described warpage as having "an outsized effect on yields in bonding processes," and characterized the DUNE 100 as "the first product of its kind in the industry, and currently has no competitors."

MeRiT AE: Preparing for Masks That Cannot Exist Yet

The third system installed at the Yongin center is the ZEISS MeRiT AE, a photomask repair tool representing the next generation of ZEISS's existing MeRiT LE platform. Its presence at the center as a prototype signals something important about where ZEISS's development attention is focused.

Photomasks are the templates through which lithography systems project circuit patterns onto silicon wafers. EUV photomasks work differently from their predecessors: rather than transmitting light through a patterned chrome layer, they reflect EUV light from a multilayer stack of alternating molybdenum and silicon, with the circuit pattern defined in a tantalum-based absorber layer above. Because EUV photons are absorbed by everything — glass, air, any solid matter — the masks operate under constraints that conventional photomask repair tools were not designed to address.

As the industry transitions to High-NA EUV — ASML's next-generation scanner platform, which uses a numerical aperture of 0.55 versus today's 0.33, enabling feature sizes well below 10 nanometers — the tolerances on photomask defects tighten further. The absorber layers are thinner, the features smaller, and the energy budget for repair even more constrained. The MeRiT AE is designed specifically for this environment, offering expanded capability to repair the smallest critical defects at the yields required for High-NA production.

Having it at the Yongin center before High-NA EUV enters high-volume production gives Korean mask shops early access to the tool in a customer-adjacent environment — shortening the qualification cycle by the same mechanism the other two tools exemplify.

Joint Evaluation Programs: How the Co-Location Model Works

The cleanroom is not just an equipment showroom. The operational model ZEISS is building around it — what the company calls Joint Evaluation Programs — is what makes the center more than a distant satellite office.

Under the JEP model, engineers from Samsung, SK hynix, or other Korean customers work alongside ZEISS engineers at the Yongin facility to evaluate tools against real production samples: actual HBM stacks, actual packaging substrates, actual process challenges specific to the customer's integration scheme. The findings from those evaluations are transmitted to ZEISS headquarters in Oberkochen, Germany, where the company's central SMT engineering organization can incorporate them into development cycles.

"R&D findings generated through collaboration with customers will be shared with ZEISS headquarters in Germany," said Hentschel. "That process allows us to develop semiconductor manufacturing technologies tailored to customer needs more quickly, and once the equipment reaches sufficient technological maturity, it can be transferred to customers' production fabs."

The architectural point is the compression it achieves: instead of a feedback cycle measured in international shipping timelines and time-zone gaps, ZEISS and its Korean customers are now in the same building. In a manufacturing regime where process nodes advance on two-year cycles and qualification windows are measured in months, that compression is materially significant.

ZEISS says it plans to make significant investments in the center over the next decade, with the specific scale and timeline of any expansion to be determined by customer demand. "If our localized R&D collaboration model proves successful with Korean customers, we can expand the center in the future," said Wilson. "However, the scale and timeline of any expansion have not yet been finalized."

ZEISS Inside Every Scanner That Matters

To understand why ZEISS's geographic positioning matters beyond the immediate customer-service benefits, it helps to understand the company's structural position in the supply chain that the Yongin center is designed to serve.

Carl Zeiss SMT, the ZEISS subsidiary responsible for the semiconductor business, is the sole manufacturer of the optical systems at the core of ASML's EUV lithography scanners. ASML holds a 24.9% minority stake in Carl Zeiss SMT, acquired in 2016 for €1 billion, cementing a strategic partnership that has been ongoing for more than 30 years. Every EUV scanner that Samsung, SK hynix, or any other chipmaker buys from ASML contains optics manufactured exclusively by ZEISS in Germany. The EUV scanner's production ramp is constrained in part by ZEISS's capacity to manufacture the more demanding High-NA optics sets for the next-generation platform. The two companies' product roadmaps are effectively one roadmap.

The transition to High-NA EUV — which ASML is ramping toward high-volume production — is the next inflection point in this dependency. High-NA scanners use a 0.55 numerical aperture optical system requiring entirely new mirror and lens geometries, fabricated to tolerances measured in fractions of a nanometer. That engineering challenge is being solved at ZEISS's facilities in Oberkochen, Jena, and Wetzlar. But the tools that must inspect, measure, and repair the masks and wafers those scanners will eventually process — tools like the NLX-100, DUNE 100, and MeRiT AE — are now being developed in active collaboration with the Korean fabs where High-NA EUV will first be put to work at scale.

For ZEISS, the Yongin center validates a model that may travel to Taiwan, Japan, or the United States in subsequent years. Korea's combination of leading-edge logic and memory fabs, a government actively accelerating semiconductor buildout, and two anchor customers of the highest strategic importance makes it a logical first test case. SK hynix holds an estimated 56% of the global HBM market and is the primary memory supplier for Nvidia's AI accelerator lineup; Samsung is simultaneously the world's largest chipmaker and the leading HBM4 challenger. Together, they represent the highest concentration of advanced packaging volume anywhere on earth — and therefore the highest concentration of demand for the specific tools ZEISS has just placed on their doorstep.

Why Equipment Suppliers Are Moving Closer

The Yongin center reflects a broader structural shift playing out across the semiconductor capital equipment industry. As chipmakers press into sub-2nm territory and advanced packaging formats such as HBM stacking and CoWoS become central to AI system performance, the feedback loops between equipment suppliers and fabs are compressing. Geography, once a secondary concern in equipment partnerships, is becoming a competitive variable.

A key dimension of this shift is that the bottleneck in AI chip supply is no longer only wafer fabrication capacity. Industry analysts and executives have consistently identified HBM packaging capacity — the assembly step that bonds multiple DRAM dies into a stack and connects the stack to the processor via an interposer — as the tighter near-term constraint on how fast AI accelerator supply can scale. The tools ZEISS has positioned in Yongin address precisely that packaging constraint: 3D inspection of stacked structures, warpage correction during bonding processes, and mask repair for the lithography nodes that define each DRAM layer's dimensions.

That alignment between what ZEISS makes and what the Korean fabs most urgently need is not coincidental. It is the strategic logic that makes co-location, at this specific moment, more than a customer-service upgrade. The ZEISS Semiconductor Korea Innovation Center's 350 square meters in Yongin are, in effect, where the next generation of AI memory yield is going to be improved — before the rest of the world sees the tool.

Frequently Asked Questions

What is ZEISS's role in semiconductor manufacturing, and why does it matter for AI chips?

ZEISS Semiconductor Manufacturing Technology manufactures the optical systems — mirrors and lenses fabricated to sub-nanometer tolerances — that sit at the core of every ASML EUV lithography scanner ever built. EUV scanners are used to pattern the most advanced semiconductor nodes, and ASML is the only company that produces them. ASML holds a 24.9% minority stake in Carl Zeiss SMT. Because ZEISS optics are the physical foundation of EUV lithography, and because EUV lithography is required to manufacture advanced AI chips, ZEISS's tool-development decisions have direct consequences for how fast the AI hardware supply chain can advance. The tools at the Yongin center — metrology, wafer flattening, and mask repair — address the specific yield challenges that arise when building HBM, the memory type inside every major AI accelerator.

What is 3D X-ray laminography, and why does dose control matter at advanced packaging nodes?

Laminography is an X-ray imaging technique adapted for flat, extended objects like 300mm semiconductor wafers. Unlike standard CT scanning, which would require rotating the wafer perpendicular to the X-ray beam — impractical at wafer scale — laminography tilts the rotation axis to capture volumetric images without distorting the sample geometry. In advanced packaging, such as HBM stacking, the critical defects are buried inside the chip stack: micro-bumps, through-silicon vias, and copper bond interfaces that cannot be inspected from the surface. X-ray laminography can image these internal structures non-destructively. The engineering challenge is dose: producing higher-resolution images requires more radiation, which can damage the chip being inspected. At hybrid copper bonding nodes, where feature dimensions are in the single-micron range, this tradeoff becomes acute — which is why ZEISS designed the NLX-100 with precise radiation dose control as a core engineering requirement rather than an afterthought.

How does the DUNE 100 correct wafer warpage without chemical-mechanical polishing?

Standard chemical-mechanical polishing (CMP) uses a slurry and polishing pad to grind a wafer's surface flat. CMP removes material from across the entire wafer to average out height variation — it cannot selectively address a localized stress pattern without affecting adjacent areas that were already within specification. As HBM stacking adds more DRAM dies to a package, differential thermal expansion and material stress generate complex, non-uniform bow patterns that CMP handles inefficiently. The DUNE 100 instead measures the wafer's exact three-dimensional shape in high precision, then applies a targeted corrective stress — using a localized process without chemical consumables — that counteracts the specific deformation pattern. The result is warpage correction in a single step, applicable to both global bow and local die-level distortion, without the contamination risk of slurry chemistry. ZEISS describes it as the first tool of its kind on the market.

What is the Joint Evaluation Program model, and why does it compress development timelines?

Under ZEISS's JEP framework at the Yongin center, engineers from Korean customers work alongside ZEISS engineers on live production samples — actual HBM stacks, real packaging substrates — in the Yongin cleanroom. Previously, this collaboration required shipping wafers internationally, waiting for results across time zones, and navigating customs logistics. The JEP model eliminates that friction entirely: customer-specific process data is generated on-site, fed back to ZEISS headquarters in Germany in near real-time, and incorporated into development cycles without the latency of international logistics. In an industry where tool qualification windows are measured in months and process nodes advance on roughly two-year cycles, compressing the feedback loop between supplier and fab from weeks to days is a material competitive advantage — both for ZEISS in refining its tools and for Korean chipmakers in qualifying those tools for high-volume production.