Huawei has published a preprint paper detailing the foundational principles of the τ (Tao's) Law, along with empirical data from the Kirin 2026 chip. This law marks a departure from traditional process scaling by integrating logic folding technology, which enables the vertical stacking of circuits through 3D hybrid bonding. This approach significantly reduces signal routing distances. The Kirin 2026 chip boasts a 55% increase in transistor density. At the same performance level, the power consumption of the NPU, GPU, and large CPU cores has been reduced by 66%, 58%, and 41%, respectively. The chip also operates at lower temperatures and offers dual modes for power saving and peak performance. The paper acknowledges that the DSP module of the Kirin 2026 chip initially faced challenges related to increased power density per unit area, but these have been addressed in the subsequent Kirin 2027 model. Furthermore, the paper introduces a hardware-based counterpart to Amdahl's Law, underscoring that the τ Law represents a time-scaling principle and that maintaining low temperatures is a deliberate design choice. Looking ahead, Huawei is committed to advancing chip technology innovation.