Samsung Electronics has reaffirmed that it will begin mass production of its 1.4-nanometer process in 2029, and unveiled an enhanced SF1.4+ node for 2030, as it works to keep pace with TSMC and Intel at the leading edge.

Shin Jong-shin, who heads design platform development at Samsung's foundry business, said at the SAFE Forum at the company's Seocho headquarters that SF1.4 is progressing smoothly toward a 2029 target for leading-edge customers, according to The Elec, with SF1.4+ to follow in 2030.

A Reaffirmation That Doubles as a Credibility Reset

The context matters as much as the dates. Samsung had originally targeted 1.4nm for 2027 when it laid out the roadmap in 2022, but pushed it to 2029 last year amid weak utilization and losses in its foundry business, choosing to stabilize its 2nm yields first. So reaffirming 2029 is partly about restoring confidence in a timeline that has already moved once. The revised schedule trails TSMC — which plans its 1.4nm-class A14 for 2028 — but roughly matches Intel, which is pursuing risk production of its 14A process in 2028 and full production in 2029. In other words, Samsung is not racing to be first; it is trying to arrive with cleaner yields than it managed early in the 2nm generation, and to compete on value rather than raw timing.

Lever One: "Plus" Nodes and DTCO

Two technical ideas run through Samsung's presentation, and both are about extracting more from a node rather than simply reaching the smallest one. The first is the "plus" node. In Samsung's naming, "SF" is the foundry process, the number is the node, and a plus sign marks an improved version. The improvement comes largely from design-technology co-optimization (DTCO) — tuning the chip's design rules and the manufacturing process together rather than separately — and Shin said "plus" nodes boost yield and PPA (performance, power, area) while preserving existing IP, so customers gain without having to redesign their chips.

Samsung put numbers on it: moving from SF2 to SF2P improved power by 26% and frequency by 15%, with more than half of that coming from DTCO. The company expects DTCO to matter more as nodes shrink and wiring and design constraints grow more complex, forcing design and process to be optimized together from the start.

Lever Two: On-Chip SRAM for AI Chips

The second lever is on-chip SRAM, which Samsung framed as a competitive edge for AI chips. SRAM is a fast type of memory that holds data as long as it's powered and, unlike DRAM, needs no periodic refresh — and integrating a large amount of it directly on the processor die shortens the distance data has to travel, improving both the performance and the power efficiency of AI computation.

Shin illustrated the trend with a striking contrast: while Nvidia's Rubin GPU integrates about 128MB of SRAM per die, a recent language-processing unit built on Samsung's 4nm process packs more than 500MB — a product understood to be from Groq. He expects that direction to accelerate as AI workloads increasingly reward keeping more memory close to the compute.

The 2nm Roadmap and the Partner Ecosystem

Samsung also detailed its 2nm roadmap, which evolves through SF2, SF2P, and SF2P+ — the third-generation node targeted for mass production in 2027–2028 — followed by SF2X, a version customized for AI and high-performance computing that also aims to preserve existing IP so customers can reuse their design assets.

The company showcased work with domestic design partners as well: AD Technology is preparing a Samsung-2nm-based AI infrastructure platform, Gaonchips is running 2nm AI and HPC projects, CoAsia Nexell is developing an advanced-packaging platform aimed at high-bandwidth memory and high-speed interfaces, and Semifive is building a 3D-IC-based logic-and-memory integration solution. Rebellions, meanwhile, presented its REBEL-100 AI accelerator, which is in mass production on Samsung's 4nm process — crediting Samsung's process and design ecosystem as important to bringing the chip to production.

Frequently Asked Questions

When will Samsung make 1.4nm chips?

Samsung has reaffirmed that mass production of its 1.4nm process, SF1.4, is targeted for 2029, with an enhanced version, SF1.4+, planned for 2030. The company announced the timeline at its SAFE Forum. It's worth noting this is a target that has already shifted once: Samsung originally aimed for 2027 when it set out the roadmap in 2022, then pushed it to 2029 last year to focus on stabilizing its 2nm yields first.

How does Samsung's 1.4nm compare to TSMC and Intel?

Samsung's 2029 target trails TSMC, which plans its 1.4nm-class A14 process for 2028 — about a year ahead. It roughly matches Intel, which is pursuing risk production of its 14A process in 2028 and full-scale production in 2029. Samsung has acknowledged it is not aiming to be first to the node, and is instead emphasizing yield quality and design-ecosystem support to compete.

What is a "plus" node?

In Samsung's foundry naming, "SF" stands for the Samsung Foundry process and the number indicates the node generation, while a plus sign marks an improved version — for example, SF2P is an enhanced SF2, and SF1.4+ will be an enhanced SF1.4. The improvements come largely from design-technology co-optimization (DTCO), which tunes chip design and manufacturing process together to raise yield and PPA (performance, power, area) while preserving a customer's existing IP, so no full redesign is required. Samsung said the SF2-to-SF2P step improved power by 26% and frequency by 15%, more than half of it from DTCO.

Why does on-chip SRAM matter for AI chips?

SRAM is a fast memory that retains data while powered and doesn't need the periodic refresh that DRAM does. Integrating a large amount of it directly onto a processor die shortens the distance data must travel between memory and compute, which improves both the speed and the power efficiency of AI calculations. Samsung highlighted the trend by contrasting Nvidia's Rubin GPU, with about 128MB of SRAM per die, against a 4nm language-processing unit (understood to be a Groq chip) that integrates more than 500MB — and said it expects on-chip SRAM capacity to keep growing as AI workloads demand it.