Samsung Electronics has notched a notable advance in cutting-edge chip research, demonstrating a vertically stacked transistor — a "3D Stacked FET" that piles transistors atop one another instead of laying them out on a plane — at the smallest gate pitch the industry has reported.

The work, by the Logic TD team at Samsung's Semiconductor R&D Center, won Best Paper at VLSI Symposium 2026, one of the field's top three conferences alongside IEDM and ISSCC, held in Hawaii from June 14–18. Samsung said the paper scored 8.29 out of 10 among more than 1,000 submissions.

From Side-by-Side to Stacked

Transistors are the switches that determine a chip's performance, and the industry has kept improving them by reshaping how current flows — from planar designs to FinFET to today's gate-all-around (GAA) structures. Samsung's paper goes a step further, taking transistors that sat side by side on a flat plane and stacking them vertically.

The approach belongs to the same family as the complementary FET (CFET) that rivals are pursuing — and the race is genuinely three-way. At the same VLSI conference, Intel demonstrated a CFET inverter at a 45-nanometer gate pitch, while Samsung pushed the gate pitch — the lateral spacing between transistor gates — down to 42nm from a previous best of 48nm, which it says makes it the smallest yet. TSMC has demonstrated comparable structures of its own. All three leading chipmakers converging on vertical stacking is the real signal: it is widely regarded as the next step on the logic roadmap once planar scaling and GAA run out of room.

Borrowing a Trick From Memory

Vertical stacking is a concept borrowed from memory, where Samsung's own V-NAND flash and HBM break through area limits by stacking cells and chips. Bringing it to logic has outsized implications: stacking the two transistors in a CMOS pair roughly halves the area they occupy, in principle doubling how many fit on a wafer of the same size. Because power efficiency scales with transistor count per unit area, Samsung says the structure can double efficiency and, in theory, deliver up to a 100% performance gain in a single step — against the roughly 15% improvement a conventional node generation brings.

Those last figures are Samsung's theoretical projections, not measured results from a production chip, and the gap between them and a shipping product is where the hard engineering lives. The central difficulty in a stacked device is electrically isolating the two transistors so the structure does not leak current, and then fabricating the whole stack at a yield high enough to be worth manufacturing. Samsung's claimed advance is largely about clearing those obstacles at a tighter pitch than anyone has reported.

A Win at a Pointed Moment

Samsung said the vertical structure "opens a new path for advancing next-generation logic semiconductors" by fitting more transistors into the same footprint. The recognition also lands at a delicate time: Samsung's foundry business has struggled with yields and customer losses as its gap with TSMC widened, and while a Best Paper does not fix a fab, it signals that the engineering talent remains — a counterpoint as the company targets a return to foundry profitability in 2028.

That is the honest measure of the news. The award is evidence that Samsung can do leading-edge logic research as well as anyone in the world; whether it can turn that research into manufacturable, profitable nodes that win back customers is the separate, harder question its foundry still has to answer.

Frequently Asked Questions

What is a 3D Stacked FET?

A 3D Stacked FET is a transistor structure that places the two transistors of a CMOS pair on top of each other vertically, rather than side by side on a flat surface. Samsung's version belongs to the broader complementary FET (CFET) family that the leading chipmakers are all developing. Stacking the pair roughly halves the chip area it occupies, which in principle allows more transistors in the same space.

How is it different from gate-all-around (GAA) transistors?

Gate-all-around transistors, used in today's most advanced chips, improve performance by wrapping the gate fully around a stacked set of channels, but the N-type and P-type transistors still sit next to each other on the plane. A 3D Stacked FET goes further by stacking those two transistors vertically, saving floor area. It is generally seen as the next major step on the logic roadmap after GAA.

What is "gate pitch," and why does 42nm matter?

Gate pitch is the lateral spacing between neighboring transistor gates; a smaller pitch packs transistors more tightly. Samsung says it reduced the gate pitch of its stacked transistor to 42 nanometers, down from a previous best of 48nm, which it claims is the smallest reported. At the same VLSI conference, Intel demonstrated a CFET inverter at a 45nm gate pitch.

Does this mean Samsung's chips will be twice as efficient soon?

Not soon, and not automatically. The roughly doubled density and efficiency, and the "up to 100%" performance figure, are Samsung's theoretical projections for the structure, not measured results from a production chip. Turning a research demonstration into a manufacturable, high-yield process takes years, and Samsung's foundry is separately targeting a return to profitability in 2028.