Samsung Electronics vice chairman Jun Young-hyun met Nvidia CEO Jensen Huang in Seoul on Monday in what the Samsung chip chief described as the best conversation the two companies have had in their long partnership — and the agenda showed why: the two sides covered not only Samsung's plan to supply HBM4 and SOCAMM memory this year but also a joint roadmap extending to HBM4E, HBM5, and, in a detail that goes beyond memory, Samsung Foundry's candidacy to manufacture Nvidia's next-generation Groq LP40 inference chip.

The meeting took place at the Shilla Hotel in Seoul's Jangchung-dong district, hours after Huang had attended an SK Group event at Seorin headquarters where he described SK hynix as Nvidia's largest memory partner. Jun stood in for Samsung Chairman Lee Jae-yong, who was traveling abroad, and it was his first direct meeting with Huang during the CEO's four-day South Korea visit.

Jun's response to the SK hynix characterization was measured but deliberate. Samsung, he said, would prove itself through results rather than through statements.

Samsung HBM4E Samples Already at Nvidia: What the Memory Roadmap Covers

On the memory side, Jun said Samsung's immediate priority is delivering sufficient volumes of two specific products this year: HBM4, the sixth-generation high-bandwidth memory it became the first company in the world to mass-produce in February 2026, and SOCAMM2, a low-power LPDDR5X memory module designed for the Vera CPU in Nvidia's Vera Rubin rack-scale AI platform.

Samsung began shipping the industry's first 12-layer HBM4E samples to major global customers, including Nvidia, on May 29 — just three months after HBM4 entered mass production. Those samples achieve a stable pin transfer speed of 14 Gb/s, scalable to 16 Gb/s, and deliver bandwidth of up to 3.6 TB/s per stack — more than 20 percent above HBM4's 11.7 Gb/s production rate. Samsung disclosed the figures in an official press release timed to the sampling announcement.

HBM4E is built on the same architectural foundation as HBM4: Samsung's 6th-generation 10nm-class (1c) DRAM process for the memory dies, combined with a 4nm logic base die manufactured by Samsung Foundry. That base-die integration distinguishes Samsung's HBM architecture from SK hynix's approach: SK hynix uses TSMC to fabricate its HBM base die, which carries a roughly 30 percent manufacturing cost premium at that process node. Samsung's vertical integration — designing, packaging, and manufacturing the base die in-house — eliminates that cost and gives it direct control over the logic layer that governs the entire stack's throughput and power behavior.

The base die is not merely a packaging decision. Under the JEDEC JESD270-4 HBM4 specification, finalized in April 2025, the standard doubled the memory interface width from the 1,024-bit bus in HBM3 to 2,048 bits, and doubled the number of independent channels per stack from 16 to 32, each divided into two pseudo-channels. Those 32 channels are managed through the logic base die, which handles memory controllers, ECC logic, and refresh circuitry. A more capable logic die — in terms of process efficiency and thermal handling — directly expands the bandwidth ceiling the stack can sustain. Samsung's ability to use a 4nm base die it fabricates internally, rather than procuring one from an outside foundry, is the engineering mechanism behind its cost structure and its control over HBM4E performance specifications.

For the longer term, the two sides discussed what Jun called "long-term cooperation plans" beginning next year, covering HBM4E volume supply and HBM5 — the eighth-generation high-bandwidth memory Samsung debuted in mock-up form at Computex 2026. Samsung intends to build HBM5's base die on a 2-nanometer process, a step intended to sustain the bandwidth and power efficiency progression into the next AI accelerator generation after Vera Rubin.

Analysts at KB Securities estimate that securing a volume HBM4E supply deal with Nvidia could add $8 billion to $10 billion in annual revenue to Samsung's memory business. Jun did not confirm whether a formal long-term supply agreement had been signed, telling reporters Samsung would spare no effort to support Nvidia's success as a key partner.

Samsung Foundry Targets Groq LP40 Work Against TSMC

The meeting's most structurally significant element may be what happened on the foundry side of the conversation. Jun confirmed that Samsung is currently manufacturing two classes of Nvidia-ecosystem chips on its foundry lines: autonomous-driving processors and the Groq LP30 — the third-generation Language Processing Unit that Nvidia deployed as part of its Vera Rubin inference architecture after closing a $20 billion asset-acquisition and licensing deal with Groq in December 2025.

The LP30 runs on Samsung's 4-nanometer process. At GTC 2026 in San Jose in March, Huang unveiled the Groq 3 LPX — the rack-level inference product built around the LP30 — as a seventh component of the Vera Rubin platform, designed to pair with the platform's 72 Rubin GPUs to handle the decode-heavy portion of agentic AI workloads. Groq 3 LPX racks were scheduled for availability in the second half of 2026.

The LP30 is an inference-specific chip that operates on an architectural principle fundamentally different from the GPU it sits alongside. Where Nvidia's Rubin GPU carries 288 GB of HBM4 memory for throughput-heavy training and prefill operations, the LP30 uses 230 MB of on-chip SRAM with 80 TB/s internal bandwidth, governed by a statically-scheduled, deterministic pipeline — what Groq's architecture documents call a programmable assembly line. Data movement across the chip is scheduled at compile time rather than runtime, eliminating the resource-contention delays that slow GPU decode under latency-sensitive inference workloads. The result is a chip purpose-built for the step that modern AI users actually experience: the response generation phase that follows a query.

Jun's June 8 remarks extended that relationship. According to reporting by Seoul Economic Daily and confirmed by TrendForce, Samsung is in discussions with Nvidia to manufacture the LP40 — the next-generation Groq chip. Industry analysts had expected TSMC to capture that order given its advanced packaging lead, but Jun's confirmation of active negotiations positions Samsung as a genuine contender. Samsung Foundry President Han Jin-man has stated publicly that the company's 4nm process is "by no means inferior," and the talks covered cooperation on next-generation process nodes as well.

If Samsung wins LP40 manufacturing, it would establish the company — which has worked to rebuild foundry credibility after losing ground to TSMC on yield reliability in recent years — as a proven supplier of leading-edge inference silicon inside Nvidia's own architecture. That outcome would matter to the broader semiconductor industry: Nvidia currently relies on TSMC for the Rubin GPU dies at the center of Vera Rubin's compute performance, and supply-chain diversification for even one component in the inference stack reduces concentration risk for the AI data center ecosystem.

How Samsung Vera Rubin Memory Supply Stacks Up Against SK Hynix

Industry analysts estimate Samsung holds approximately 25 to 30 percent of the HBM4 volume allocated for Vera Rubin, with SK hynix at roughly 60 to 70 percent and Micron taking the remainder. Nvidia has not published official allocation figures. Huang arrived in Seoul on June 5 and confirmed at the airport that all three vendors had passed qualification and were in active production for Vera Rubin, with the first customer shipments scheduled for Q3 2026 to major cloud platforms including AWS, Google Cloud, Microsoft Azure, and Oracle.

The volume gap between SK hynix and Samsung reflects a qualification-timeline advantage SK hynix established on the HBM3 and HBM3E generations. TrendForce estimated before Computex 2026 that SK hynix would hold approximately 50 percent of global HBM bit output for the year, with Samsung's share rising to approximately 28 percent.

Samsung's ability to reclaim share in the HBM5 generation — where the company is first to demonstrate the architecture and plans to use an in-house 2nm base die — may determine whether the current allocation gap is structural or cyclical.

What Is HBM4 and Why Does Architecture Matter for AI Workloads?

High-bandwidth memory achieves its speed advantage over conventional DRAM by stacking up to 16 memory dies vertically above a logic base die, connecting them through thousands of microscopic through-silicon vias (TSVs), and placing the assembled stack beside the GPU on a silicon interposer. This arrangement cuts the distance data must travel between memory and compute from centimeters to micrometers, allowing HBM4's 2,048-bit interface to feed data to Rubin GPUs at speeds that would require a prohibitively wide circuit board trace if attempted with conventional discrete memory.

The practical consequence for AI workloads is direct: training a trillion-parameter language model requires moving model weights between memory and compute billions of times per second. Each successive HBM generation narrows the gap between how fast the GPU can compute and how fast memory can supply it with data — a gap the industry calls the memory wall. HBM4's 2 TB/s per stack, delivered via 32 independent channels each running at 8 Gb/s under the JEDEC JESD270-4 specification, roughly doubles the throughput HBM3E provided.

Jun's June 8 comments indicate Samsung has already completed the engineering work on HBM4E's 4nm base die and is ready to move to mass production on customer timelines. What the meeting did not produce — and what analysts are watching for — is a formal long-term supply agreement. Jun declined to confirm whether one had been signed.

Frequently Asked Questions

What did Samsung and Nvidia discuss in their June 8, 2026 Seoul meeting?

Samsung vice chairman Jun Young-hyun met Nvidia CEO Jensen Huang on June 8, 2026, at the Shilla Hotel in Seoul to discuss the full scope of their semiconductor partnership. Near-term topics included ensuring stable supply of HBM4 memory and SOCAMM2 modules for Nvidia's Vera Rubin platform this year. Longer-term discussions covered HBM4E and HBM5 supply starting in 2027, foundry cooperation on advanced process nodes, and Samsung Foundry's potential role manufacturing Nvidia's next-generation Groq LP40 inference chip.

How is Samsung HBM4E different from HBM4?

Samsung's HBM4E delivers a stable pin transfer speed of 14 Gb/s, scalable to 16 Gb/s, and bandwidth of up to 3.6 TB/s per 12-layer stack — more than 20 percent faster than HBM4's 11.7 Gb/s production rate. Both chips share the same 6th-generation 1c DRAM process and 4nm logic base die from Samsung Foundry, but HBM4E incorporates design and process optimizations that improve energy efficiency by 16 percent and reduce thermal resistance by more than 14 percent compared with HBM4.

Is Samsung or SK hynix the bigger Nvidia HBM supplier?

SK hynix is currently Nvidia's largest memory partner, as Huang stated publicly on June 8, 2026, and analysts estimate it holds roughly 60 to 70 percent of HBM4 supply allocated for Vera Rubin. Samsung holds an estimated 25 to 30 percent share, with Micron taking the remainder. Samsung's June 8 meeting with Huang covered the steps it intends to take to grow that share in the HBM4E and HBM5 generations.

What is Samsung's role in Nvidia's Groq inference chip supply chain?

Samsung Foundry currently manufactures the LP30 — the third-generation Groq Language Processing Unit, sold as the Nvidia Groq 3 LPX — on its 4nm process. After Nvidia acquired Groq's assets and key personnel for $20 billion in December 2025, the LP30 became a core component of the Vera Rubin platform, pairing with Rubin GPUs to handle low-latency AI inference decode. As of June 8, Samsung is in active discussions to also manufacture the next-generation LP40, though no formal agreement has been announced.