A week after TSMC committed $265 billion to Arizona and announced dedicated advanced packaging capacity there, a new analysis from Semiconductor Engineering lays bare what that announcement also confirmed: the United States, despite its unprecedented investment, still cannot finish its own AI chips at home. Every accelerator built at TSMC's Phoenix fab travels to Taiwan for CoWoS packaging before it can ship — and that will remain true for at least two more years. That is the concrete policy gap at the center of a global semiconductor race that, as of July 2026, has fractured into four fundamentally different national strategies, each betting on a different layer of a supply chain that no single country fully controls.

US Betting on Wafer Fabs, Missing the Finishing Step

The CHIPS Act funding of $53 billion in direct funding, plus tax credits, catalyzed a stunning expansion of American silicon fabrication capacity. The crown jewel is TSMC's Fab 21 campus outside Phoenix, where Phase 1 has reached approximately 92% yield on 4nm production — by one report, slightly above yields at comparable TSMC facilities in Taiwan. Phase 2, targeting 3nm production, completed construction in April 2026 and began equipment installation in the third quarter of 2026, with volume production now pulled forward to 2027.

The total US commitment has now reached $265 billion across 12 planned facilities — the largest foreign direct investment in American history — following TSMC CEO C.C. Wei's announcement at the company's Q2 2026 earnings conference in Taipei on July 16.

But there is a structural gap that the investment scale obscures. TSMC currently sends virtually all of its chips to Taiwan for packaging — including those manufactured at its advanced Phoenix facility. The specific bottleneck is CoWoS — Chip on Wafer on Substrate — the 2.5D advanced packaging process that every major AI accelerator on the market depends on to function as a shippable product.

What CoWoS Actually Does, and Why the US Doesn't Have It Yet

CoWoS is not a refinement of wafer fabrication. It is a separate manufacturing step that places a logic die — a GPU or custom AI accelerator — alongside multiple stacks of High-Bandwidth Memory (HBM) on a silicon interposer: a thin slab of silicon containing high-density metal interconnects and through-silicon vias that route data between the components at speeds and bandwidths physically impossible to achieve on a conventional circuit board. Every NVIDIA H100, H200, Blackwell-generation GPU, and AMD MI300-series accelerator ships on CoWoS packaging. Without it, a fabricated AI chip die is not a salable product.

TSMC's CoWoS capacity was expanding toward 120,000 to 140,000 wafer starts per month by the end of 2026 — a roughly fourfold increase from late 2024 — at a compound annual growth rate exceeding 80% between 2022 and 2027, according to TrendForce data. Yet demand continues to outpace supply. At his Q2 2026 earnings conference, Wei publicly acknowledged that CoWoS remains fully sold out, with lead times now exceeding one year.

Advanced packaging facilities are planned for Arizona. TSMC announced dedicated CoWoS capacity as part of its July 16, 2026 commitment, and Amkor Technology — working with Apple and NVIDIA — is separately targeting its Arizona facility for production start in early 2028. TSMC's own Arizona packaging operation is targeting 2029. The implication is clear: the United States' most consequential sovereignty gap is not in wafer fabrication, where tens of billions in CHIPS Act spending have made real progress. It is in packaging — the finishing step that is equally critical to AI chip delivery and has remained, until now, an afterthought in domestic semiconductor strategy.

The European Court of Auditors captured a parallel dynamic in its 2025 special report on the EU Chips Act: in the rush to fund wafer fabs under Pillars I and II, advanced packaging — the supply chain's actual AI bottleneck — received comparatively little structural attention. The packaging blind spot is not unique to the US; it is a shared policy failure across the Western semiconductor sovereignty programs.

UK: Precision Strike Over Moonshot

Where Washington has gone big and broad, London has gone targeted and deliberate.

The AI Hardware Plan, announced by Technology Secretary Liz Kendall at London Tech Week on June 8, 2026, sets out how the government will back British companies developing the chips and semiconductor technologies behind AI, while also investing in the scientists, engineers, and technicians needed to turn new ideas into products and good jobs in the UK. The plan centers on a £750 million (approximately $999 million) national AI supercomputer to be built at the University of Edinburgh, with deployment targeted for 2030, of which £400 million (approximately $533 million) is designated for next-generation AI chips. A £120 million (approximately $160 million) AI Hardware Innovation Programme will support startups developing advanced semiconductor technologies, helping companies move from research to commercial deployment.

The strategy reflects an explicit and rational rejection of the full-stack rebuild approach. Fabs can cost more than $20 billion apiece and take years to bring online — making a complete domestic semiconductor industry an unrealistic use of capital for a mid-sized economy. Instead, the UK is doubling down on design IP. The UK's Council for Science and Technology analysis concludes that the UK has differentiated strengths across a range of AI-enabling semiconductor technology areas, including as headquarters of Arm, whose architecture is present in many of the most cutting-edge AI chips and is now producing its own CPU chip for agentic AI.

Kendall has signaled she will not accept the argument that the hardware race has already been won by the US and Taiwan, positioning the UK as a potential winner not in manufacturing volume, but in the design IP and architectural layers that sit above it — the part of the stack that generates the highest margins.

The skills pipeline is being explicitly built: the Semiconductor skills program has been expanded to £48 million (approximately $64 million), growing undergraduate bursaries from 300 in academic year 2025–26 to 400 in 2026–27 and 500 in 2027–28, alongside a new £12 million (approximately $16 million) Centre for Doctoral Training in Chip Design. One substantive risk: as analysts have noted, the UK strategy's execution still relies heavily on non-UK hardware in the near term — AMD chips power the Cambridge DAWN supercomputer upgrade, and recent Nebius deployments use NVIDIA hardware. Building compute capacity and building genuine IP ownership of the underlying technology stack are distinct challenges that the plan has not yet fully bridged.

EU: From Volume Target to Strategic Indispensability

The European Union's chip strategy has undergone the most visible philosophical recalibration of any major economy.

The original 2023 European Chips Act set a target of bringing the EU's share of global semiconductor production from roughly 10% to 20% by 2030, anchored by a €43 billion (approximately $48.9 billion) investment framework. In April 2025, the European Court of Auditors delivered a pointed verdict: meeting the 20% target would require approximately quadrupling EU production capacity by 2030, "but we are nowhere close to that with our current rate of progress," auditor Annemie Turtelboom said. Europe's market share stood at 9.8% in 2022 and is projected to reach only 11.7% by 2030 — well below the target.

The original Chips Act did succeed in mobilizing more than €52 billion (approximately $59.2 billion) in public and private investment, creating an estimated 46,000 direct and indirect jobs, and strengthening Europe's research and innovation capacity in semiconductors. Despite that progress, the EU remains dependent on third countries in key areas such as advanced chip manufacturing and semiconductor design. The European Commission's response, unveiled on June 3, 2026, is the proposed Chips Act 2.0, which forms part of the broader Technology Sovereignty Package and aims to accelerate permitting procedures with approvals targeted within a maximum of 12 months, and launch "Grand Challenges" to support industrial development of strategic technologies including AI chips.

The more revealing shift is strategic: rather than doubling down on the volume target, EU policy is now explicitly oriented toward "strategic indispensability" — occupying the segments of the chip supply chain where European firms have genuine competitive moats. GlobalFoundries' general manager and senior VP for Europe, Manfred Horstmann, put it to EE Times: European firms hold real strengths in automotive chips, power semiconductors, payments chips, and specialty processing. Chasing the hyperscaler segment, which requires the most advanced nodes and the deepest capital pools, doesn't strategically make sense. "Don't invest in stuff where we can only lose," Horstmann said. "Invest in stuff where we can win."

That logic is now embedded in EU policy. The Chips Act 2.0 is designed to both reinforce current European strengths, including mainstream chips, and build capacity in cutting-edge semiconductor technologies — allowing the EU to maintain its position as an indispensable player in the value chain while strengthening its resilience and reducing strategic dependencies.

India: Building the Stack for the First Time, With Global Positioning

India's position is distinct from the other three in one fundamental way: where the US is trying to restore manufacturing capacity it once had, India is building it for the first time.

The launch of India Semiconductor Mission 2.0 in the Union Budget 2026–27 marks a decisive shift from ecosystem creation to ecosystem consolidation and global integration — deepening support for manufacturing, design, and advanced skills while positioning semiconductors as a central strategic national capability. The government has set aside ₹1,000 crore (approximately $104 million) for FY 2026–27, with a strong emphasis on industry-led research and training centers. Longer-term targets include achieving 3nm and 2nm node capability by 2035 and expanding the fabless startup base to 50 companies.

The talent pipeline is a central pillar. Lam Research signed a partnership with ISM and IIM to train 60,000 semiconductor engineers in fabrication technologies over 10 years. More than 315 Indian universities have been equipped with state-of-the-art EDA tools, with over 68,000 specialized engineers trained so far. Independent analysts caution that documented challenges remain: India's supply chain still depends heavily on imported semiconductor equipment, specialty gases, and raw materials — making the ecosystem vulnerable to supply disruptions and foreign export-control risks.

Crucially, India's approach is not purely inward-looking. Prime Minister Narendra Modi has explicitly named semiconductors as a key pillar of India's partnership with the EU, framed around a new free trade agreement and planned investment agreement. Dutch foreign minister Tom Berendsen has articulated the complementarity directly: "India brings enormous engineering talent, innovation capacity, and growing manufacturing ambitions. That is a very powerful combination with the Netherlands' advanced ecosystem." India is building domestic capability while simultaneously positioning itself as a preferred partner in a redistributing global supply chain — rather than trying to wall off a sovereign corner of it.

Tata Electronics is setting up India's first commercial silicon fabrication foundry in Dholera, Gujarat, in a multi-billion-dollar partnership with Taiwan's PSMC, aiming for first silicon output by late 2026.

What No Country Has Figured Out — and Why It Matters

Technological sovereignty, properly understood, does not mean a complete domestic semiconductor supply chain. It means strategic control over the chokepoints that matter most. As analysts have noted, technological sovereignty is considered distinct from autarky — it seeks to avoid full dependencies on critical technologies, not to eliminate all interdependencies. That distinction has profound implications for how to evaluate each of the four strategies — and for which is best calibrated to its actual strategic objective.

The Semiconductor Engineering analysis, published as a sponsor blog post by Nandan Nayampally, chief commercial officer at Baya Systems, makes the point plainly: no economy runs a complete semiconductor stack, not even the United States. Every policy framework is ultimately trying to answer the same three questions: what do we need to control domestically, where are we comfortable being interdependent, and how much capital are we willing to commit?

The most revealing answer to those questions is not in the investment totals. It is in what each strategy left uncovered. The US funded wafer fabrication at historic scale but left domestic packaging — CoWoS and the AI chip finishing layer — running until 2028 or later through Taiwan. The EU mobilized €52 billion ($59.2 billion) but is projected to land at 11.7% global market share by 2030, not 20%, because the funding proved insufficient to overcome years of manufacturing concentration elsewhere. The UK deliberately exempted itself from the fab race and is betting that design IP is worth more per dollar invested — a sound thesis that remains unproven at scale. India is building from the ground up, with the most transparent gap of any of the four (no leading-edge domestic fab yet) but also the most globally integrated posture.

Each bet shapes where TSMC, Samsung, and Intel Foundry will build capacity in the next decade. And each will interact with — and in some cases redirect — the trillion-dollar investment flows that CHIPS Act-style subsidies have set in motion. The packaging gap that currently limits US semiconductor sovereignty is not just a technical problem. It is also a policy signal every other major economy is watching, and planning around: even a $265 billion commitment cannot substitute for getting the strategic priorities right from the start.

Frequently Asked Questions

Why does the US still depend on Taiwan for chip packaging, even after the CHIPS Act?

The CHIPS Act's $53 billion in direct funding was primarily directed at wafer fabrication — the step that produces raw silicon chips. Advanced packaging, the separate manufacturing stage that assembles logic dies with High-Bandwidth Memory into functional AI accelerator packages, received comparatively little direct investment. As a result, even though TSMC's Fab 21 in Phoenix is producing 4nm chips at approximately 92% yield, virtually all of those chips still travel to Taiwan for CoWoS packaging before they can ship. Domestic US CoWoS capacity — from Amkor Technology's Arizona facility and TSMC's own planned packaging fabs — is not expected to begin production until at least 2028. The gap reveals a structural miscalibration: advanced packaging, not wafer fabrication, is the actual binding constraint on AI chip supply.

What is the EU's realistic semiconductor outlook after Chips Act 2.0?

The original Chips Act's 20% global market share target by 2030 has been independently assessed as highly unlikely to be achieved. The European Court of Auditors found in its 2025 Special Report that meeting the target would require quadrupling EU production capacity by 2030 — far beyond the pace of investment to date. Europe's share is projected to reach only 11.7% by 2030, up from 9.8% in 2022. Chips Act 2.0, proposed in June 2026, reflects a more realistic strategic reorientation: rather than chasing volume share at advanced nodes, the EU is now explicitly targeting "strategic indispensability" — competitive dominance in the niche segments where European firms already lead, including automotive chips, power semiconductors, and payments chips.

Is India's semiconductor strategy realistic, and what are the biggest obstacles?

India Semiconductor Mission 2.0 sets ambitious targets — 3nm and 2nm node capability by 2035, 50 fabless startups, and 60,000 trained fabrication engineers through Lam Research partnerships — but analysts identify structural risks. India's semiconductor supply chain currently depends heavily on imported equipment, specialty gases, and raw materials, making it vulnerable to supply disruptions and export-control risks from major suppliers. The ₹1,000 crore (approximately $104 million) FY 2026–27 allocation is comparatively modest against the capital requirements of leading-edge fabrication. India's near-term competitive advantage is more credibly in advanced packaging, outsourced semiconductor assembly and testing (OSAT), and fabless chip design, where capital requirements are lower and engineering talent is a clearer differentiator.

What does "semiconductor sovereignty" actually mean, and is any country achieving it?

Semiconductor sovereignty, properly defined, does not mean a complete domestic supply chain — it means avoiding full dependencies on critical chokepoints. No country runs a complete semiconductor stack today: the US relies on TSMC for leading-edge wafer manufacturing and Taiwan for advanced packaging; Europe relies on ASML (Netherlands) for EUV lithography equipment and on foreign foundries for advanced nodes; the UK relies on non-UK hardware for its supercomputers; India has no leading-edge domestic fab. The real competition is over strategic indispensability — who gets to be the irreplaceable link in a supply chain that must remain globally distributed. By that standard, the most strategically sound posture may be the EU's explicit reorientation toward segments where European firms cannot be easily replaced, rather than the US approach of funding full-stack rebuild at historic cost.