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Alice & Bob became the first quantum hardware company to demonstrate a non-Clifford gate on cat-qubit hardware, the startup confirmed on October 20, 2026, in Phase 1 results from PROQCIMA — France's €500 million (approximately $561 million USD) national quantum computing competition. The same Phase 1 results showed the company running multiple cycles of a three-qubit repetition code on real chips and measuring the logical error rate across its full twelve-qubit register. That error rate remains above the fault-tolerance threshold — the point at which error-correction overhead begins paying off in measurably lower logical error rates — making these results a component validation rather than a demonstration of fault-tolerant operation. They are also, by the standards of what the program required in Phase 1, precisely the kind of rigorous, measurable, on-hardware milestones the competition was designed to surface.

Why the Non-Clifford Gate Is the Specific Missing Ingredient

Understanding why the non-Clifford gate result carries so much weight requires a brief detour into quantum computing's most fundamental constraint on universality. Quantum error-correcting codes can protect a standard set of operations — called Clifford gates (H, S, CNOT) — while keeping them transversal and relatively inexpensive. The Gottesman-Knill theorem shows that Clifford-only circuits can be efficiently simulated classically, which means a quantum computer restricted to Clifford gates cannot outperform a classical computer on problems of interest, no matter how error-free its operations become. To achieve universal quantum computation, every fault-tolerant architecture requires at least one additional operation from outside the Clifford group — typically a T gate or equivalent. These non-Clifford operations cannot be made transversal without violating the Eastin-Knill theorem, so they must be implemented through a workaround: "magic states," specially prepared ancilla qubits that, when consumed via state injection, produce the effect of the non-Clifford gate on the logical qubit.

This means every serious fault-tolerant quantum computing architecture requires a "magic state factory" — a subsystem that distills high-fidelity magic states from many noisy copies — running in parallel with the main computation. For conventional transmon-based architectures using surface codes, magic state factories are notoriously expensive, consuming hundreds of times more space-time overhead per T gate than a Clifford operation. One of the theoretical advantages of the cat-qubit approach is that the noise-biased error profile is expected to make magic state factories substantially more efficient: the bit-flip suppression that makes the repetition code viable also simplifies the factory architecture.

Alice & Bob's Phase 1 non-Clifford gate demonstration establishes the experimental baseline for that factory — what the company describes as "a first step toward producing the 'magic states' [the architecture] requires." No prior cat-qubit hardware implementation had demonstrated this gate on chip. The milestone completes the ingredient list: noise-biased CNOT gates, syndrome extraction, repetition code error-correction cycles, logical error rate measurement, and now a non-Clifford gate — all demonstrated on superconducting cat-qubit hardware rather than simulated.

What the Three Demonstrators Actually Showed

Alice & Bob assembled and operated three independent hardware systems to satisfy Phase 1's feasibility requirements: two six-qubit superconducting chips and one twelve-qubit chip. Across these platforms, the team demonstrated each building block of its cat-qubit logical-qubit architecture:

Noise-biased CNOT gates between cat qubits. The fundamental challenge of performing gate operations on cat qubits while preserving their noise bias is that the gate itself must not introduce symmetric errors that would undermine the built-in bit-flip suppression. Executing CNOTs that preserve the bias is a non-trivial engineering requirement, and demonstrating them on chip — not in emulation — is a measurable step.

Measure-and-reset sequences. The company demonstrated auxiliary qubit syndrome readout and then re-prepared those qubits for the next correction cycle, performing broadly in line with program targets. This is the fundamental repetitive cycle that quantum error correction requires: measure what went wrong, reset the ancilla, repeat.

A distance-3 repetition code run over multiple cycles. The company ran multiple rounds of a three-data-qubit repetition code — the smallest code capable of correcting a quantum error rather than merely detecting one. Sustaining multiple error-correction cycles on hardware is a prerequisite for the prolonged computations that would be practically useful.

Logical error rate measurement. The team measured the logical error rate across the full chip register, a capability required to track progress toward fault tolerance. The result: above threshold. Alice & Bob has described this candidly rather than obscuring it, a transparency consistent with the program's accountability requirements.

A non-Clifford gate on a cat qubit. As discussed above, this is the architectural first.

What the Digital Twin Found

Alongside the hardware results, Alice & Bob built a digital twin of its processors from the measured performance data of the actual chips. Running forward-looking simulations on this model, the team identified the specific improvement that would most reduce logical error rates: coherence uniformity. Not simply extending the peak coherence time of the best-performing qubits on a chip, but extending it consistently across all qubits. A chip where some qubits outperform others in coherence creates asymmetric error rates that the repetition code cannot correct as efficiently as a chip where all qubits behave identically. This is the company's explicitly stated next engineering priority before the system can cross the error-correction threshold.

The demonstrators were supervised around the clock by Alice & Bob's proprietary MnR monitoring and recalibration software, which tracked more than 50 performance indicators per qubit and automatically triggered recalibration when the quantum processing unit was idle. The system significantly reduced the time spent identifying and correcting performance drift — a previously manual process that could consume a full day of operating time per qubit.

How This Fits PROQCIMA's Updated Target

PROQCIMA launched in March 2024 with a target of 128 logical qubits by 2032 and a 2,048-logical-qubit commercial system by 2035. In May 2026, the French government substantially upgraded the program: President Macron announced an additional €1 billion (approximately $1.12 billion USD) in quantum investment through the France 2030 framework, the Phase 2 budget was doubled, and the primary logical-qubit target was raised from 128 to 1,024 by 2032. The 2035 target of 2,048 logical qubits remains unchanged.

Phase 2 of PROQCIMA (2026–2028) is a €150 million (approximately $168 million USD) phase — €30 million (approximately $34 million USD) per company — at the end of which only three of the five competing companies will advance. For Alice & Bob, the Phase 1 results are the primary evidence submitted for that selection. Phase 1 was designed to test technical and industrial feasibility on actual hardware, not to require below-threshold operation — and on that standard, delivering five distinct component demonstrations (including the first non-Clifford gate on cat-qubit hardware) across three independently assembled chips is a substantive showing.

The other four competing architectures — Pasqal's neutral atoms, Quandela's photonic qubits, Quobly's silicon CMOS spin qubits, and C12's carbon-nanotube approach — have each been building toward their own Phase 1 milestones on parallel tracks, with the same selection deadline. France's bet is not on any single architecture; it is on the race itself surfacing the approach that can reach 1,024 logical qubits by 2032. Alice & Bob's cat-qubit claim is that the noise-biased error profile reduces the physical-qubit overhead required to reach that target by a factor of up to 200 compared with conventional transmon surface-code approaches — a theoretical figure confirmed in the architecture's design, not yet in the integrated system's measured performance, but now anchored to actual chip results for all five individual building blocks.

What the Above-Threshold Result Actually Tells Researchers

An above-threshold logical error rate is an important data point rather than a failure. It means the system is currently in the regime where the error-correction overhead — the additional operations needed to run the repetition code — adds more noise than it removes. Below the threshold, the reverse becomes true: more cycles of error correction produce exponentially lower logical error rates, enabling the long, reliable computations that practical algorithms require. Alice & Bob's Phase 1 system is on the correct side of the architectural question — all the building blocks function as intended — but not yet on the correct side of the quantitative threshold.

The digital twin's identification of coherence uniformity as the specific bottleneck is more useful to the field than a bare statement that the error rate is above threshold. It names a precise engineering target: not "make qubits more coherent in general" but "make coherence uniform across all qubits on the chip simultaneously." That is a fabrication and materials science problem as much as a circuit design problem, and one that Alice & Bob's €50 million ($56 million USD) quantum cleanroom in Paris — opened in March 2026 — is designed to address.

CEO Théau Peronnin framed results in competitive terms: "The race for fault-tolerant quantum computing is a question of who will master one of the defining technologies of this century, and France starts from a position of real strength. Our PROQCIMA Phase 1 results show that the cat-qubit approach, combined with Alice & Bob's expertise, can lead that race and push the frontiers of science."

Context: AWS Validated the Architecture, Alice & Bob Is Building the Machine

Alice & Bob is not the only team pursuing cat qubits. Amazon Web Services published Ocelot cat-qubit chip results in early 2025, demonstrating error suppression across a three-to-five-cat-qubit array and claiming up to 90% overhead reduction compared to conventional approaches. Alice & Bob's research scientist David Schlegel noted in commentary at the time that AWS's approach suppresses bit-flip errors significantly, while Alice & Bob's architecture targets complete elimination of bit-flips — a distinction that, if achievable at scale, implies more than tenfold further reduction in qubit count. The two organizations are pursuing the same foundational physics from different directions: AWS from the cloud infrastructure angle, Alice & Bob from the dedicated fault-tolerant hardware angle with the stated goal of a 1,024-logical-qubit PROQCIMA-compliant system by 2032.

Separately, Alice & Bob has been selected for DARPA's Quantum Benchmarking Initiative, which independently evaluates whether quantum computing architectures can reach industrially useful fault-tolerant operation by 2033 — a timeline that runs in parallel with, and will provide external validation of, the PROQCIMA milestones. The company also signed an HPC integration agreement with Bull to integrate its cat-qubit systems with high-performance computing infrastructure — acknowledging that near-term useful quantum computation will almost certainly arrive as hybrid classical-quantum workflows rather than standalone quantum operation.

How Cat-Qubit Error Correction Works at the Physics Level

For readers who want to understand what the company is actually building: a cat qubit encodes quantum information in the superposition of two coherent states of a microwave resonator — labeled |α⟩ and |-α⟩, analogous to Schrödinger's famous alive-and-dead superposition. In Alice & Bob's superconducting implementation, a storage resonator couples through a nonlinear element (the ATS, or asymmetrically threaded SQUID) to a lossy buffer mode. This coupling mediates a process called two-photon driven dissipation: only photon pairs can exchange between the memory resonator and the buffer, never single photons. Because a bit-flip error requires a single-photon event — the jump from |α⟩ to |-α⟩ — it is structurally forbidden by the engineered dissipation, and the probability of one occurring decreases exponentially as the average photon number in the resonator grows.

The tradeoff is precise: phase-flip errors are not suppressed and increase linearly with photon number. But this asymmetric error profile is exactly what makes the one-dimensional repetition code sufficient. A conventional transmon qubit suffers both bit-flip and phase-flip errors at comparable rates, requiring a two-dimensional surface code that scales quadratically in physical qubit overhead. Cat qubits reduce error correction from a quadratically scaling two-dimensional problem to a linearly scaling one-dimensional problem — and that difference is where the claimed 200x overhead reduction originates, according to Guillaud and Mirrahimi's 2019 Inria paper in Physical Review X.

The Phase 1 results demonstrate that this architecture functions as designed at the component level on real superconducting chips. The question now is whether coherence uniformity — the specific gap the digital twin identified — can be closed across an integrated multi-qubit system before the Phase 2 selection deadline.

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Frequently Asked Questions

What is a non-Clifford gate and why does demonstrating one on cat-qubit hardware matter?

Clifford gates — a standard set of quantum operations including the Hadamard, phase (S), and CNOT gates — can be efficiently simulated by a classical computer, which means a quantum computer restricted to them cannot outperform classical hardware on problems of interest. Adding any one non-Clifford gate, such as the T gate, makes the combined set universal: any quantum algorithm can be approximated by circuits built from it. However, non-Clifford gates cannot be made transversal (applied directly to logical qubits) without violating fundamental error-correction constraints, so fault-tolerant architectures instead implement them using "magic states" — specially prepared ancilla qubits that, when consumed via state injection, produce the effect of the non-Clifford gate. Alice & Bob's Phase 1 result demonstrates a non-Clifford gate on cat-qubit hardware for the first time, establishing the experimental baseline for designing its cat-qubit magic state factory — the subsystem every universal fault-tolerant quantum computer requires to run real algorithms.

Why is the logical error rate being above threshold important information, not just a failure?

An above-threshold logical error rate means the system is currently in the regime where running error correction adds more overhead noise than it removes. Below the threshold, the reverse is true: more correction cycles produce exponentially lower logical error rates, enabling sustained computations. Alice & Bob's Phase 1 system demonstrates all five architectural building blocks working on chip — the non-Clifford gate, noise-biased CNOTs, syndrome extraction, multi-cycle repetition code, and logical error rate measurement — while the above-threshold result identifies exactly what to fix next: coherence uniformity across all qubits simultaneously. A system that honestly measures and reports its threshold position is in a better engineering position than one that only reports favorable individual component metrics.

What is PROQCIMA and how does Alice & Bob's Phase 1 standing affect what happens next?

PROQCIMA is a €500 million (approximately $561 million USD) French government quantum computing competition managed by the Defense Innovation Agency and the Direction Générale de l'Armement, selecting five companies — Alice & Bob, Pasqal, Quandela, Quobly, and C12 — to develop competing qubit architectures. France's government raised the primary target in May 2026 from 128 to 1,024 logical qubits by 2032, doubling the Phase 2 budget to €150 million (approximately $168 million USD) total. In Phase 2 (2026–2028), only three of the five companies will advance based on demonstrated hardware maturity. Alice & Bob's Phase 1 results — submitted as evidence for that selection — document the first integrated multi-chip demonstration of every cat-qubit error-correction building block, including the first non-Clifford gate on cat-qubit hardware, while candidly reporting that the logical error rate is not yet below the fault-tolerance threshold.

How close is any quantum computer to breaking modern encryption?

No quantum computer today can run Shor's algorithm at the scale required to break RSA or elliptic-curve cryptography. Running Shor's algorithm on a 2,048-bit RSA key would require millions of physical qubits operating below fault-tolerance threshold — a capability that remains years away on any current trajectory. However, nation-state adversaries are already collecting encrypted data today with the intent to decrypt it once such a machine arrives — a strategy documented by NIST, the UK's National Cybersecurity Centre, and the G7 Cyber Expert Group. The pace of progress represented by results such as Alice & Bob's Phase 1 milestones is directly relevant to how quickly organizations need to migrate to post-quantum cryptographic standards. France has set a 2030 mandatory deadline for that migration across critical infrastructure.