Six manufacturing partners. Three countries. One governing constraint: capacity. At GTC Berlin on Wednesday, NVIDIA named the companies and disclosed the dollar figures that will determine whether Vera Rubin AI factories can ship at volume — anchored by a $1.1 billion advance to chip tester King Yuan Electronics (KYEC) for new US facilities and a planned 15x optics capacity increase at Taiwan's Siliconware Precision Industries (SPIL).

"We are in the midst of the largest infrastructure buildout in human history. Demand is extraordinary. Capacity is the constraint," said NVIDIA founder and CEO Jensen Huang in his GTC Berlin statement. The remark was characteristically blunt — and characteristically precise. The six agreements announced Wednesday represent the most detailed public accounting NVIDIA has given of the manufacturing bottlenecks standing between today's GPU orders and tomorrow's AI factory deployments.

The numbers are striking in context: NVIDIA's Q2 FY2027 10-Q shows supply and capacity commitments totaling $279 billion as of July 26, 2026, up from $119 billion a quarter earlier. Each agreement announced at GTC Berlin is a named piece of that aggregate — and together they trace the full back-end manufacturing chain from optical-engine packaging through chip testing to finished substrates.

SPIL Builds the Optical Engine Layer — 15x by Mid-2027, 30x by 2028

The most technically demanding agreement involves SPIL, the Taiwan-based advanced-packaging subsidiary of ASE Group. NVIDIA and SPIL are targeting a 15x optical-engine capacity increase for optical engines used in co-packaged optics by mid-2027, with a further doubling — reaching 30× today's baseline — by the end of 2028.

Co-packaged optics (CPO) is the technology at the center of NVIDIA's Vera Rubin networking architecture. In a traditional pluggable-transceiver design, electrical signals must travel 15 to 30 centimeters along PCB traces before reaching the optical module, losing enough fidelity that a DSP retimer must regenerate the signal before it can be converted to light. That retimer consumes power and introduces latency. In a CPO design, the optical engine sits inside the same package as the switch ASIC, reducing the electrical path to millimeters — too short to need equalization. The DSP retimer is eliminated entirely, cutting power consumption by approximately 70% compared to pluggable alternatives. NVIDIA's Spectrum-6 switch leverages CPO to reach 102.4 Tb/s Ethernet bandwidth — a ceiling that copper-based switching cannot approach at equivalent power.

The SPIL agreement adds the manufacturing layer to that architecture. Optical engines are not assembled like pluggable transceivers. They must be built with photonic integrated circuits (PICs) and electronic integrated circuits (EICs) co-packaged at the wafer level, with precision fiber arrays attached at submicron tolerances. That process is far more specialized than inserting a discrete module into a front-panel cage — it is why a 15× ramp over 18 months is considered ambitious in the industry, and why NVIDIA appears to have begun securing the partnership well in advance.

At GTC Berlin, NVIDIA described its Spectrum-6 CPO switch as the primary networking building block for Vera Rubin DSX AI factory scale-out, citing the SPIL capacity agreement as central to bringing co-packaged optics to the AI data center at volume.

KYEC: $1.1 Billion Advance, Chip-Testing Capacity Doubles by 2027

For chip testing — the final gating step before any GPU or networking ASIC can ship to a customer — NVIDIA turned to King Yuan Electronics, the world's largest pure-play semiconductor test house. NVIDIA is advancing $1.1 billion to KYEC as a capacity reservation payment, funding construction of new semiconductor testing facilities and equipment in the United States, with high-volume production at those US sites targeted for April 2027.

A separate Singapore expansion is expected to reach high-volume production in February 2027, two months ahead of the US ramp. Taken together, NVIDIA expects chip-testing capacity to double across its US, Taiwan, and Singapore operations between calendar year 2026 and 2027.

The $1.1 billion figure represents roughly 0.4% of NVIDIA's $279 billion in aggregate supply commitments, but its strategic weight is disproportionate: doubling testing capacity is a direct multiplier on how many finished Vera Rubin GPUs and Spectrum-6 ASICs can actually reach customers in a given quarter. No other manufacturing step can compensate if testing is the bottleneck.

Substrate Tier: Three Countries, 2.5× Aggregate by 2028

Substrates — the high-density organic interposers that carry electrical signals between chip dies and printed circuit boards — represent a quieter but equally critical constraint. NVIDIA announced that agreements with three substrate suppliers across Japan, South Korea, and Taiwan are expected to deliver a 2.5x substrate capacity increase over the next three years.

Taiwan's entry is Unimicron Technology Corporation, one of the world's largest substrate manufacturers. Under a capacity reservation agreement, NVIDIA is supporting Unimicron's KF substrate expansion of its Kyocera-format, high-density ABF manufacturing lines. The new capacity is expected to begin contributing in Q2 2027 and reach full build-out by mid-2028.

In Japan, IBIDEN — a longstanding supplier of ABF substrates for high-end processors — is receiving a multibillion-dollar advance from NVIDIA (exact amount undisclosed), with additional capacity targeted to ramp beginning in Q1 2028. In South Korea, Samsung Electro-Mechanics is formally joining NVIDIA's substrate supply, contributing capacity immediately from its existing operations.

The lead times involved here are worth noting explicitly. ABF substrate capacity additions require two to three years from capital investment to qualified production volume — meaning that the agreements NVIDIA announced Wednesday are the decisions that will determine substrate availability not just for Vera Rubin but for the platform generation that follows it. These are generational manufacturing commitments, not product-cycle adjustments.

Amkor: More Than 300% Advanced Packaging Capacity by End of 2028

Rounding out the six-partner announcement is Amkor Technology, the US-headquartered advanced-packaging specialist with significant Asia operations. NVIDIA said Amkor plans to increase packaging capacity over 300% by the end of 2028, providing an additional manufacturing lane for the complex assembly work that turns individual chip dies into finished AI accelerator modules.

Why Supply Chain Is the Story Right Now

The timing and specificity of Wednesday's disclosures are inseparable from Vera Rubin's operational status. The platform — comprising seven new co-designed chips, including the Rubin GPU, Vera CPU, and Spectrum-6 networking ASIC — is now in full production. The NVL72 configuration packs 72 Rubin GPUs and 36 Vera CPUs into a single liquid-cooled rack, delivering 3.6 exaFLOPS NVFP4 inference compute.

The companion DSX POD announcement at GTC Berlin sharpened the pressure further. NVIDIA's factory-assembled, containerized Vera Rubin NVL72 stack is designed to cut AI factory deployment time from the current five to six months to as little as 14 days. If NVIDIA can compress the time from hardware delivery to live token production that dramatically, the rate-limiter shifts entirely upstream: to how fast chips can be tested, substrates can be fabricated, and optical engines can be assembled. Every figure announced Wednesday addresses one of those upstream stages.

GTC Berlin also served as NVIDIA's primary pitch to European hyperscalers and AI factory operators. Huang noted that NVIDIA has invested approximately $10 billion across Europe over the past year. Presenting a credible supply-chain plan — with named partners, concrete dollar commitments, and milestone dates — is a commercial necessity for an audience being asked to underwrite multi-gigawatt AI infrastructure programs. NVIDIA's $279 billion in aggregate supply commitments, disclosed in its Q2 FY2027 filing, provides the scale context for Wednesday's named agreements.

Taiwan's Central Role Confirmed — and Qualified

Taken together, the six agreements confirm Taiwan's position across all three manufacturing layers Vera Rubin requires. SPIL handles the most technically novel and demanding element — CPO optical-engine packaging at a 15× target that no other region currently replicates. KYEC anchors chip-testing expansion across both domestic Taiwan operations and the new US buildout. Unimicron provides the substrate layer alongside Japanese and South Korean counterparts.

NVIDIA has made geographic diversification — adding US and Singapore test capacity, bringing Samsung Electro-Mechanics into the substrate supply chain — a consistent public theme in 2026. But the magnitude of the Taiwan-specific commitments announced Wednesday makes clear that diversification is a supplement to, not a substitute for, the island's foundational role in the AI hardware supply chain.

One caveat is worth stating explicitly: NVIDIA disclosed these as planned capacity targets, not confirmed shipment allocations or volumes reserved exclusively for Vera Rubin. The 15× and 30× SPIL figures are manufacturing-capacity goals, not shipment guarantees. The industry will be watching SPIL's mid-2027 CPO milestone, KYEC's April 2027 US production ramp, and Unimicron's Q2 2027 substrate additions as the first concrete checkpoints for whether the announced buildout is tracking to plan.

Frequently Asked Questions

What is co-packaged optics, and why does it matter for Vera Rubin?

Co-packaged optics (CPO) places optical engines — the components that convert electrical signals into light pulses — inside the same package as the networking switch ASIC, reducing the electrical path from 15 to 30 centimeters (in pluggable transceiver designs) to just a few millimeters. That short path eliminates the need for a DSP retimer chip, cutting power consumption by roughly 70% and allowing NVIDIA's Spectrum-6 switch to reach 102.4 Tb/s of Ethernet bandwidth. For Vera Rubin AI factories, which demand networking bandwidth that copper-based designs cannot sustain at the required power envelope, CPO is an architectural necessity — making SPIL's capacity expansion one of the most consequential manufacturing bottlenecks in the entire AI supply chain.

When will KYEC's $1.1 billion US facilities begin production?

NVIDIA is targeting high-volume production at KYEC's new US testing facilities beginning in April 2027. A separate expansion in Singapore is expected to reach high-volume production two months earlier, in February 2027. Together with existing Taiwan capacity, NVIDIA expects total chip-testing throughput to double from 2026 to 2027. The April 2027 US date is a target, not a contractual guarantee; the NVIDIA KYEC agreement was signed October 13, 2026.

Why are substrate lead times significant for these agreements?

ABF (Ajinomoto Build-up Film) substrates — the high-density interposers used in advanced AI accelerators — require two to three years of lead time from capital investment to qualified production volume. The three substrate partner agreements announced Wednesday will add capacity beginning in Q2 2027, Q1 2028, and immediately, respectively. Because these timelines extend well past the Vera Rubin production cycle, the investments effectively lock in substrate capacity for NVIDIA's next-generation platform as well — making them generational supply-chain commitments rather than single-product-cycle reservations.

What is the NVIDIA DSX POD, and how does it relate to these supply-chain announcements?

The DSX POD is a factory-assembled, containerized version of NVIDIA's Vera Rubin NVL72 rack stack, designed to reduce AI factory deployment time from the current five to six months to as little as 14 days. By compressing the deployment window that dramatically, NVIDIA shifts the binding constraint from on-site integration to upstream manufacturing — specifically, to how fast chips can be tested, substrates can be produced, and optical engines can be assembled. The six supply-chain agreements announced at GTC Berlin are, in part, a direct response to that shift: if deployment can be compressed to two weeks, manufacturing throughput is what determines how many AI factories can go live each quarter.