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Researchers at Japan's RIKEN Center for Emergent Matter Science have cleared one of silicon quantum computing's most stubborn engineering roadblocks — the fidelity collapse that previously happened whenever multiple qubits shared the same microwave control wire. In a study published in Nature Physics on October 15, 2026, the team demonstrated five silicon spin qubits operating in parallel on a single microwave line while holding fault-tolerant fidelity across the board, a result that directly attacks the wiring bottleneck that currently prevents silicon quantum processors from scaling to the thousands of qubits that practical computation will require.

The numbers are precise and hard to downplay. When the team ran three qubits simultaneously, every qubit exceeded 99.99% single-qubit gate fidelity — at or above the practical threshold that surface-code error correction demands. Running all five at once brought four of the five qubits above 99.9%, with the fifth approaching that mark. Both benchmarks sit at or above what quantum error correction researchers call the practical fault-tolerant threshold, the fidelity level below which error-correction overhead becomes unworkable.

The core achievement is summarized in the published arXiv preprint of the paper: all five qubits achieved primitive gate fidelities well above 99.99% when operated individually — some approaching 99.999%, exceeding previously reported benchmarks for silicon spin qubits — while fidelities at the practical fault-tolerant threshold of 99.9% were maintained even during fully parallel five-qubit operation.

Why Parallel Control Broke Silicon Qubits: The AC Stark Shift Problem

Silicon spin qubits encode quantum information in the spin state of individual electrons trapped in nanoscale structures called quantum dots, each roughly 50 to 100 nanometers across — comparable in size to a modern transistor. Controlling those spins requires microwave pulses, delivered through an impedance-controlled coaxial line routed into a dilution refrigerator that keeps the device near absolute zero. The obvious way to scale is to give every qubit its own line. The problem is that dilution refrigerators have hard limits on how many coaxial cables they can accommodate — physically, thermally, and mechanically — making individual per-qubit lines a genuine ceiling on qubit count. The engineering challenge of routing electronics into cryogenic quantum processors at scale has been recognized as a critical bottleneck for years.

Sharing one line among multiple qubits sidesteps that ceiling, but it introduced a different problem: when the microwave pulse for qubit A leaks into qubit B on the same line, it shifts B's resonance frequency through a physical effect called the AC Stark shift — also known as the Autler-Townes effect, discovered in 1955 by physicists Stanley Autler and Charles Townes, in which an oscillating electromagnetic field perturbs the effective energy levels of a nearby quantum system. In a multi-qubit array, those unwanted phase shifts accumulate with each parallel gate operation, pushing qubits off their intended trajectories and degrading fidelity precisely when simultaneous operation is needed most.

Previous attempts to run multiple silicon spin qubits in parallel on a shared line saw fidelities drop from above 99.9% down to around 99.5%, below the fault-tolerant threshold. The RIKEN team identified the AC Stark shift as the primary culprit, then devised a calibration protocol specifically designed around its mathematical properties.

Pairwise Calibration: Quadratic Overhead Instead of Exponential

The key insight behind the team's solution is that the AC Stark phase shift on any given qubit, from any given drive signal, is independent and additive: measuring how much qubit Q₃ drifts when qubit Q₄ is driven, and how much it drifts when Q₂ is driven, gives you exactly what you need to predict and cancel the drift when both Q₂ and Q₄ drive simultaneously. This linearity — confirmed in the paper's Section 1.4 — means you only need to measure pairwise interactions — N(N-1) total calibrations for N qubits — rather than characterizing every possible combination of simultaneous drives, which would grow exponentially and become impractical beyond a handful of qubits.

"Rather than requiring an entirely separate calibration procedure for every possible combination of qubits, our method uses calibrations between pairs of qubits to compensate for the unwanted phase shifts," said Yi-Hsien Wu, the paper's first author, who conducted the experiments as part of his PhD research at RIKEN.

For five qubits, that means 20 pairwise calibrations, not 2⁵ = 32 combinatorial configurations. The team verified the additive property explicitly by measuring Q₃'s phase drift while driving Q₂ and Q₄ individually, then comparing the sum of those individual measurements to the drift observed when both drove simultaneously — the agreement was precise.

Alongside the calibration protocol, the team switched from conventional rectangular microwave pulses to Kaiser-window shaped pulses — an envelope function that concentrates the pulse's spectral energy near the target frequency and dramatically reduces the broadband spectral leakage that rectangular pulses produce at their sharp edges. The two-technique approach described in the paper pushed individual single-qubit gate fidelities above 99.99% for all five qubits, with the best qubit (Q₃) reaching 99.9987% — exceeding previously reported benchmarks for silicon spin qubits.

How Sharing One Line Cuts the Wiring Problem

The architectural significance of the result runs deeper than the fidelity numbers. Impedance-controlled microwave coaxial lines are among the most challenging components to thread into a dilution refrigerator at scale. Each line adds thermal load, occupies physical space, requires individual connectors and filtering, and must maintain signal integrity from room temperature down to the millikelvin stage where qubits operate. Companies including Bluefors and Delft Circuits have developed specialized cryogenic cabling technologies specifically because standard coaxial cables become a hard physical ceiling on qubit counts — a lab-scale dilution refrigerator might fit 50 to 500 such lines before space and thermal budget run out.

A silicon quantum processor where five qubits share one microwave line requires one-fifth as many impedance-controlled lines per qubit — and the team's analysis suggests the scaling could extend to ten qubits per line at current device architecture without fidelity falling below the fault-tolerant threshold. "By addressing a key source of control errors through pairwise calibration," said co-first author Leon Camenzind, "our study supports the use of shared control lines as a practical approach to scaling up quantum processors."

"This shows that high-fidelity control can be maintained even when several qubits are operated at the same time and represents an important step toward scaling up silicon-based quantum processors," Camenzind added.

What Drive-Induced Decoherence Still Limits

The result is not a complete solution to the parallel-control problem. When all five qubits operated simultaneously, total microwave power on the shared line increased relative to three-qubit operation — and that higher power introduced additional decoherence not addressed by the phase calibration protocol. The calibration corrects for deterministic phase errors caused by the AC Stark shift. It does not correct for the stochastic loss of quantum coherence caused by microwave-induced heating of the quantum dot environment, as the paper's conclusions explicitly note.

"This is a limitation, but further improvements to device design could help mitigate this source of error," Camenzind said.

The team's analysis identifies the path forward: the current device uses a cobalt micromagnet with a 400-nanometer (about 16 millionths of an inch) gap above the quantum dot array, generating a magnetic field gradient that enables individual qubit addressability. Simulations show that narrowing the micromagnet gap to 200 nanometers could roughly double the gradient strength, enabling faster gate operations at the same or lower microwave power — which would reduce drive-induced decoherence and likely push five-qubit parallel fidelity above 99.99%. Alternatively, integrating nanomagnets directly into the gate layer — closer to the qubits — could achieve the same effect while improving layout scalability.

Silicon's Position in the Quantum Race

Silicon spin qubits have long carried the strongest long-term scaling argument of any qubit platform. Their transistor-scale footprint means that millions of them could in principle fit on a chip manufacturable with existing semiconductor foundry processes — the same production lines that build today's computer chips. Yet for years they lagged behind superconducting circuits and trapped-ion systems in demonstrating the high-fidelity operations that fault-tolerant quantum computing requires. That changed in 2022, when RIKEN, QuTech, and UNSW published back-to-back papers in Nature demonstrating silicon spin qubit gate fidelities exceeding 99% on two-qubit gates.

The new result extends that trajectory. Demonstrating that five qubits can operate in parallel above the fault-tolerant threshold — while simultaneously reducing the number of wires needed to control them — closes two separate gaps at once.

Commercial and industrial interest has followed the technical progress. IBM's acquisition of HRL Laboratories, completed after announcement in July 2026, was partly driven by HRL's silicon spin qubit intellectual property, including demonstrations of digitally controlled silicon quantum processing units built on standard 200-millimeter semiconductor wafers. Hitachi has also committed to a silicon quantum computing roadmap under Japan's JST Moonshot Goal 6 program, targeting 100 qubits by fiscal year 2028 and a 1,000-qubit-scale device by fiscal year 2030.

"Our long-term goal is to build a fault-tolerant quantum computer based on silicon spin qubits, and reliable parallel control is an essential step toward that goal," said Seigo Tarucha, project manager of RIKEN's silicon quantum computing project under JST Moonshot Goal 6, which targets a fault-tolerant universal quantum computer by 2050.

One significant limitation remains untouched by this work: two-qubit gate fidelity. The RIKEN device demonstrated here achieves below 97% fidelity for two-qubit CZ gates in the current configuration — a separate engineering challenge from the single-qubit parallel control problem this paper addresses, as the paper's methods section documents, and one the team's future work will need to resolve to demonstrate the full gate set that fault-tolerant algorithms require.

How Will This Accelerate the Path to Fault-Tolerant Silicon?

The question researchers in the field are now asking is how directly this result translates into the millions of physical qubits that a practically useful fault-tolerant quantum computer will require. The pairwise calibration protocol's quadratic scaling — 20 calibrations for five qubits, 90 for ten, 9,900 for 100 — remains manageable for unit cells of up to several dozen qubits per microwave line. But connecting thousands of such cells into a full processor is a systems-integration challenge several orders of magnitude beyond what has been demonstrated.

The paper's authors offer a specific and testable prediction: at a gate time of 500 nanoseconds, fully parallel operation of ten silicon spin qubits on a single shared microwave line should preserve fault-tolerant fidelities comparable to what five qubits achieved in this study, because the total microwave power is the same. That prediction is now a concrete near-term experimental target.

Frequently Asked Questions

What is the fault-tolerant threshold, and why does 99.9% matter?

Fault-tolerant quantum computing uses quantum error correction to suppress errors in a self-reinforcing way — but only if the underlying physical operations are accurate enough to begin with. Below a critical fidelity level called the fault-tolerant threshold, adding more error correction actually makes things worse. For the surface code, the dominant error-correction approach in the field, achieving practical fault tolerance under realistic noise conditions requires physical gate fidelities at or above roughly 99.9%. The RIKEN result cleared that bar for all five qubits simultaneously — meaning the shared-line architecture doesn't sacrifice the error-correction viability that fault-tolerant computation demands.

What is the AC Stark shift, and why has it been so hard to eliminate in silicon qubits?

The AC Stark shift is a well-understood quantum physics phenomenon: when an oscillating electromagnetic field — in this case, the microwave control pulse — drives near the resonance frequency of a neighboring quantum system, it shifts that system's energy levels. In a multi-qubit silicon array on a shared microwave line, every drive pulse for one qubit leaks slightly to its neighbors, shifting their resonance frequencies and introducing phase errors in any gates those neighbors are running simultaneously. The reason it was hard to eliminate is that the magnitude of the shift depends quadratically on drive amplitude, varies between every qubit pair, and changes sign depending on the frequency relationship between the driving and target qubits — so it cannot be pre-compensated with a single fixed correction. The RIKEN pairwise calibration protocol handles it by measuring each qubit pair's AC Stark phase shift individually and applying those individual corrections superimposed, exploiting the fact that the shifts add linearly even when multiple qubits drive at once.

How does the wiring bottleneck in dilution refrigerators constrain quantum computer scaling?

Every qubit in a conventional silicon quantum processor requires its own dedicated impedance-controlled coaxial cable running from room-temperature electronics down to the millikelvin stage of a dilution refrigerator. Those cables add thermal load, occupy physical volume, and require careful filtering and signal conditioning. A standard lab-scale dilution refrigerator can accommodate roughly 50 to 500 such lines before running out of space and cooling budget — which means a processor requiring thousands of individually wired qubits would need refrigerators of impractical size and cost. The RIKEN team's approach reduces coaxial lines required per qubit substantially, potentially extending to ten qubits per line and reducing line count by up to 80 percent, offering a more tractable path toward processors large enough to run fault-tolerant algorithms.

How do silicon spin qubits compare to superconducting qubits in the race toward fault-tolerant quantum computing?

Superconducting qubits — the technology used in processors from IBM, Google, and others — currently lead in qubit count and in the scale of quantum error correction demonstrations. They have been operating above 99% gate fidelity for several years and have demonstrated error-corrected logical qubit operations on dozens of physical qubits. Silicon spin qubits are several years behind in system scale but carry a structural advantage: their transistor-scale footprint means they can, in principle, be manufactured at chip-scale densities using existing semiconductor foundries, enabling processors with millions of qubits on a single chip — a density superconducting qubits cannot match. Recent analysis of silicon's competitive position signals that silicon is gaining serious near-term traction, supported by this result and commercial moves from IBM and Hitachi.