Samsung's chief foundry rival now manufactures the most sophisticated component inside Samsung's own flagship AI memory product — a striking collapse of the vertical integration model that Samsung's memory division has relied on for decades. Seoul Economic Daily reported Sunday that Samsung Electronics agreed to source base dies for Nvidia's proprietary NVHBM memory architecture from TSMC's 3nm process, handing the contract to the Taiwanese foundry after an internal review concluded that Samsung's SF2 process cannot match TSMC's yield rates at the scale and reliability Nvidia demands.

The decision confirms what semiconductor researchers have tracked for months: a roughly 40-percentage-point yield gap between Samsung's SF2 gate-all-around process (estimated at 50 to 60 percent) and TSMC's N3 FinFET node (above 90 percent, per Nvidia's brief to suppliers) has become disqualifying for Samsung Foundry at the top of the AI memory market.

The report also confirms that Samsung is not alone in this dependency. All three major high-bandwidth memory vendors — Samsung, SK Hynix, and Micron Technology — will source NVHBM base dies from TSMC, making the Taiwanese foundry the sole logic manufacturing partner for every premium AI memory program on Nvidia's roadmap.

What the NVHBM Architecture Changed: Why the Base Die Is Now a Logic Chip

To understand why Samsung's foundry capabilities are suddenly at the center of an AI memory decision, it helps to know what Nvidia changed when it announced NVHBM on August 26, 2026.

In every previous generation of high-bandwidth memory, the memory controller — the logic block that governs how data flows in and out of the stack — resided on the GPU or accelerator compute die itself. That means a portion of expensive, power-hungry silicon on the GPU is dedicated to memory management rather than raw computation. Nvidia's NVHBM architecture relocates the memory controller directly into the HBM base die: the bottom chip in the DRAM stack that previously served only as a passive routing and buffering layer.

Nvidia states the architectural payoff as substantial: up to 30 percent higher memory bandwidth per stack compared to the JEDEC HBM4E specification, 15 percent lower power consumption, and up to 25 percent more die area freed on the XPU compute die. Moving the physical-layer interface into the 3D stack also reduces PHY and support area on the accelerator die by up to 67 percent against the HBM4E standard.

The critical manufacturing implication: a base die that houses a full memory controller is no longer a simple routing chip. It is sophisticated logic — logic sophisticated enough to demand the same class of foundry node used to manufacture leading-edge GPUs. That is why Nvidia specified 3nm for the base die. And that is why Samsung's SF2 yield rate suddenly matters more than its DRAM capacity.

Why Foundry Yields Forced a $100 Billion Market Decision

Semiconductor yield is the percentage of chips on a wafer that pass functional testing. It is the primary lever of per-unit cost, delivery predictability, and supply reliability for any high-volume semiconductor program.

TechInsights estimates Samsung's SF2 process yields in the 50-to-60-percent range. TSMC's N3 process is achieving yields above 90 percent, according to Nvidia's brief to suppliers as reported by Seoul Economic Daily and confirmed by industry tracking of all three HBM vendors' sourcing decisions.

That gap has concrete arithmetic consequences. At 90 percent yield, a leading-edge wafer produces roughly 1.6 to 1.8 times as many working chips as the same wafer at 55 percent yield — with no difference in wafer cost. For a program requiring tens of millions of NVHBM stacks across Nvidia's Feynman GPU platform and its downstream systems, the per-unit cost differential and the supply reliability differential compound into a sourcing decision that Samsung Foundry cannot win on economics alone.

Samsung SF2's yield gap is partly structural. Samsung introduced gate-all-around transistor architecture at its 3nm node and carried it into SF2 — a generation earlier than TSMC, which begins GAA at its N2 (2nm) node. GAA process maturation typically lags FinFET maturation because the manufacturing tolerances are tighter. TSMC N3 is a mature FinFET process that has been in high-volume production longer, accumulating defect-density learning that SF2's GAA process has not yet replicated, according to semiconductor industry analysts tracking the two nodes.

The global HBM market is projected to reach roughly $100 billion by 2028, according to Counterpoint Research market data. The base die has become the component that determines which foundry wins the premium tier of that market.

Samsung's Vertical Integration Advantage: How the Narrative Collapsed

Samsung's all-in-house manufacturing model was supposed to be the advantage that separated it from SK Hynix and Micron in the NVHBM race.

The logic was straightforward: Samsung is the only major HBM vendor that operates both a memory division (designing and producing DRAM stacks) and a foundry business (Samsung Foundry, with advanced logic processes). Where SK Hynix and Micron had to coordinate across separate companies to integrate custom base die logic with their DRAM stacks, Samsung could do everything under one project team, one yield learning loop, and one packaging infrastructure.

That narrative required Samsung Foundry to be process-competitive. It was not — at least not at the yield rates Nvidia requires. Rather than accepting a dependency on its own foundry's current maturity, Samsung's memory division concluded that TSMC's process advantage is too large to cede. Keeping the NVHBM design win by outsourcing the base die to a rival is, by Samsung's calculation, better than losing it entirely by insisting on an in-house process that cannot yet meet the specification, as Samsung's own pre-deal positioning had emphasized the in-house advantage.

The report says Samsung is retaining Samsung Foundry as a fallback option. If TSMC's capacity is insufficient to meet demand — a real possibility as all three HBM vendors simultaneously request 3nm base die capacity — Samsung plans to assess whether SF2 can serve as secondary supply. That dual-track structure gives Samsung optionality without fully conceding the foundry question.

TSMC Gains a Structural Position Inside All Three HBM Vendors

Samsung's decision closes a loop that had been forming across the AI memory industry for the better part of a year.

SK Hynix, the current HBM market leader with approximately 50 percent share as of mid-2026, already operates a deep foundry relationship with TSMC for base die manufacturing. The company uses TSMC's 12nm process for mainstream server-class HBM4 base dies and is escalating to 3nm for premium designs targeting Nvidia's flagship GPU programs and Google's TPUs. SK Group chairman Choi Tae-won reaffirmed this strategy in person during meetings in Taiwan with TSMC chairman C.C. Wei and Nvidia CEO Jensen Huang in June 2026.

Micron has confirmed that both its NVHBM product and its JEDEC-standard HBM4E will use base dies from an external foundry. TSMC is the named manufacturer for Micron's HBM4E base logic die, targeting production in the first half of 2027.

The result is a market structure that would have seemed implausible two years ago: TSMC — a company that manufactures no DRAM of its own — is now the sole logic foundry for the base die layer of every premium AI memory product from every major supplier. TSMC's process maturity has inserted it structurally into a supply chain it does not anchor from the memory side, giving it leverage inside Samsung's, SK Hynix's, and Micron's product lines simultaneously.

NVHBM's Role in Nvidia's Platform Architecture

Nvidia unveiled NVHBM on August 26, 2026, as an extension of its NVLink Fusion framework — the platform that allows hyperscalers to integrate their own custom accelerators with Nvidia's networking and system-level architecture. NVHBM defines the controller and interface specification within the base chip, then sources to any qualifying memory manufacturer.

Amazon's Annapurna Labs is the first named partner. Amazon plans to support NVLink Fusion with its Trainium4 custom accelerator, enabling Amazon chips and Nvidia GPUs to operate within a shared rack-scale architecture while using NVHBM for their memory subsystem. The Trainium4 collaboration confirmed Amazon's Annapurna Labs as the first NVHBM partner under NVLink Fusion.

The multi-supplier structure of NVHBM — in which Nvidia defines the controller and interface specification within the base chip, then sources to any qualifying memory manufacturer — is designed to give hyperscale infrastructure buyers supply diversity. For customers running AI clusters at scale, the concentration risk of single-supplier memory has been a chronic procurement vulnerability. NVHBM's architecture addresses that directly, which is also why Nvidia's yield requirements are non-negotiable: the program's supply redundancy value only holds if every qualified supplier can actually deliver at volume.

Nvidia's Feynman GPU platform, expected in 2028, is planned as the first full-scale GPU deployment to adopt NVHBM. Feynman pairs with Rosa CPUs, NVLink-8 interconnects, BlueField-5 DPUs, and Spectrum-7 networking in Nvidia's fully integrated AI computing architecture.

Does Samsung's HBM Recovery Stay on Track?

The TSMC outsourcing decision arrives at a consequential moment for Samsung's memory division.

Samsung was the original dominant force in HBM, but it lost ground sharply as SK Hynix executed more cleanly on HBM3E qualification for Nvidia's Blackwell and Hopper GPU generations. By Q2 2025, SK Hynix held roughly 64 percent of the HBM market, Micron had grown to approximately 21 percent, and Samsung had fallen to around 15 percent, according to Counterpoint Research market tracking. Samsung has since partially recovered: by Q2 2026, its share had risen to approximately 33 percent as HBM4 production ramped, with SK Hynix at 50 percent and Micron at 18 percent.

Samsung began HBM4 mass production in February 2026 at initial speeds of 11.7 Gbps, and is targeting volume shipments of HBM4E samples in the second half of 2026. The company has added 250 engineers to its custom HBM development teams specifically targeting programs from Google, Meta, and Nvidia, and is in the backend design stage for its HBM4E base die.

Custom HBM — and NVHBM specifically — remains Samsung's most direct path to recapturing high-value AI compute business. Accepting a foundry dependency on TSMC keeps Samsung in contention for the NVHBM program rather than conceding it entirely to SK Hynix and Micron. The more consequential question is whether Samsung Foundry can close the yield gap in time to become the primary SF2 supplier rather than the backup.

Samsung's 2nm SF2 process is still maturing. Whether that maturation arrives before Nvidia's Feynman platform requires locked-in base die commitments — likely in 2027 — will determine whether Samsung's foundry eventually recaptures the base die win it has just given to TSMC, or whether TSMC's structural position inside Samsung's own product hardens into a long-term dependency.

Frequently Asked Questions

What is a base die in HBM memory, and why does its foundry node matter?

The base die is the bottom chip in a high-bandwidth memory stack. In earlier HBM generations, it handled simple routing and physical-layer interfacing between the DRAM stacks above it and the GPU below it — a relatively modest logic job that could run on older process nodes. Nvidia's NVHBM architecture changes that by placing a full memory controller inside the base die. A chip that houses an advanced memory controller is no longer simple routing logic; it is sophisticated computing circuitry that demands the same leading-edge foundry node used to manufacture GPUs. That is why TSMC's 3nm process — rather than a DRAM-era manufacturing node — is required, and why foundry yield rates at that process node became the deciding factor in Samsung's sourcing decision.

Why is Samsung using TSMC instead of its own Samsung Foundry for the NVHBM base die?

Samsung Foundry's SF2 gate-all-around process is estimated to be achieving yields in the 50-to-60-percent range. TSMC's N3 FinFET process is achieving yields above 90 percent. At Nvidia's scale, a 40-percentage-point yield gap means TSMC produces roughly 60 to 80 percent more working chips per wafer at similar cost — with corresponding advantages in supply reliability and delivery schedule. Samsung's memory division concluded that insisting on SF2 would risk losing the NVHBM design win to SK Hynix and Micron, both of which already use TSMC for base die manufacturing. Outsourcing to a foundry rival is a calculated trade: it keeps Samsung in Nvidia's premium AI memory program while Samsung Foundry continues to mature its process.

Does this mean TSMC now controls the AI memory supply chain?

TSMC does not manufacture DRAM — the actual memory cells that store data in HBM stacks are still produced by Samsung, SK Hynix, and Micron at their own DRAM fabs. What TSMC now controls is the base die layer: the logic chip at the bottom of every premium NVHBM stack, from all three vendors simultaneously. That is a structurally significant position. TSMC's process maturity has made it indispensable to a supply chain it does not anchor from the memory side, giving it leverage inside each HBM vendor's flagship AI memory product. How durable that position is depends on whether Samsung SF2 can close the yield gap before Nvidia's Feynman platform locks in base die commitments in 2027.

When will Nvidia's NVHBM chips actually appear in production AI hardware?

Nvidia's Feynman GPU platform is expected in 2028 as the first full-scale deployment of NVHBM. Feynman is planned to integrate with Rosa CPUs, NVLink-8 interconnects, BlueField-5 DPUs, and Spectrum-7 networking in Nvidia's integrated AI computing stack. Before Feynman, NVHBM will appear in the NVLink Fusion context — Amazon's Annapurna Labs is the first named partner, planning to support NVHBM via its Trainium4 custom accelerator in mixed Nvidia-Amazon rack-scale configurations. Micron's TSMC-manufactured HBM4E base dies are targeting production in the first half of 2027, suggesting NVHBM supply chains will be in volume ramp ahead of Feynman's 2028 target.