Keysight Technologies has introduced FITS-16CH, a 16-channel digital-layer error performance validation system designed for next-generation 800G and 1.6T optical and copper interconnects. The new platform doubles the transmit and receive channel density of Keysight’s existing FITS-8CH system, enabling engineers to characterize complete interconnect assemblies across development, qualification, manufacturing, and AI data center deployment. The system supports 106G and 212G lane-rate validation for high-speed interconnects.

The new Functional Interconnect Test Solutions (FITS)-16CH platform combines bit error ratio (BER) measurements with forward error correction (FEC) analysis to evaluate interconnect reliability beyond traditional electrical and optical physical-layer compliance testing. Its 16 transmit and 16 receive channels support testing through two module compliance boards with independent channel groups and controls. The system supports full-retimed optics (FRO), active optical cables (AOCs), linear-retimed optics (LRO), linear pluggable optics (LPO), active copper cables (ACCs), active electrical cables (AECs), passive direct attach cables (DACs), and high-speed copper flyover connections. Keysight positions the platform for both component-level engineering and complete-assembly qualification, including testing through lossy channels and customer-specific fixtures.

Keysight has also expanded automation capabilities to reduce the time required to optimize high-speed electrical links. FITS-16CH integrates with Keysight’s DCA-X analyzers to automate transmit finite impulse response (FIR) tap adjustments, improving electrical eye openings and accelerating lane tuning. The platform can operate alongside Keysight bit error ratio testers and UXR real-time oscilloscopes, with SCPI-based automation, real-time measurement visualization, pass/fail reporting, and PDF or CSV output. Credo Technologies, a supplier of high-speed connectivity solutions and active electrical cables, highlighted the importance of validating complete AEC assemblies as signal margins tighten at 1.6T speeds.

Key Takeaways

Executive Commentary

Ameet Suri, Vice President of Product at Credo Technologies, emphasized the importance of system-level testing as electrical margins tighten at 1.6T.

“The tighter margins at 1.6T make it essential to evaluate active electrical cable performance at the system level, not in isolation for each link.”

Suri said Keysight’s testing capabilities help Credo identify potential AEC performance issues earlier during development and qualification. Ram Periakaruppan, Vice President and General Manager of Network Test & Security Solutions at Keysight, said the expanded platform addresses the need to validate more lanes simultaneously across multiple interconnect technologies while reducing laboratory complexity.

Analysis: Why Digital-Layer Validation Matters at 1.6T

The transition from 800G to 1.6T Ethernet is increasing the importance of system-level error performance testing, particularly as AI data centers deploy a wider combination of optical and copper interconnects.

At 1.6T, eight electrical lanes operating at approximately 200 Gb/s each must maintain adequate signal integrity across connectors, cables, retimers, and other components. PAM4 signaling increases spectral efficiency but reduces the separation between signal levels compared with NRZ signaling, making link performance sensitive to insertion loss, reflections, crosstalk, and equalization settings.

Physical-layer compliance testing establishes whether electrical and optical interfaces meet specified characteristics. However, passing those measurements does not necessarily establish how an assembled interconnect will behave over extended operating periods or under realistic channel conditions. BER and FEC measurements provide additional information about error performance and correction margins. These measurements become especially important when evaluating different combinations of host silicon, cables, connectors, and optical modules.

Keysight’s FITS-16CH addresses this validation stage by providing simultaneous measurements across 16 transmit and 16 receive channels. The increased channel count also has implications for manufacturing throughput, where vendors must qualify growing volumes of 800G and 1.6T interconnect assemblies.

Copper Remains Important in AI Scale-Out Networks

Although optical connectivity is essential for longer-reach data center connections, copper continues to serve short-reach links where cable length, power consumption, cost, and signal integrity requirements permit. Passive DACs avoid the additional active electronics used in retimed cables, while AECs and ACCs incorporate signal-conditioning technologies to extend usable copper connectivity under more demanding electrical conditions.

At 200G-per-lane signaling rates, the tradeoffs between passive copper, active copper, and optical connectivity become increasingly dependent on actual channel conditions and system architecture. Credo’s participation highlights the relevance of these measurements for suppliers developing active electrical cable solutions. The ability to measure BER and FEC behavior across complete assemblies provides data for optimizing retimer settings, evaluating cable performance, and determining operating margins.

Keysight’s broader 1.6T portfolio also includes Ethernet traffic generation, network performance testing, and physical-layer compliance instruments. FITS-16CH occupies a complementary position by focusing on functional error performance of assembled interconnects, rather than replacing compliance or network traffic testing.

The principal development is the expansion of interconnect qualification from individual electrical and optical measurements toward repeatable, multi-lane validation of complete assemblies.

Company Profile: Keysight Technologies