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GlobalFoundries unveiled FDX Fusion on October 9 — a fully depleted silicon-on-insulator chip platform designed to deliver 7nm-class digital performance for autonomous vehicles, industrial robots, drones, and smart sensors, without the extreme-ultraviolet lithography that every other sub-10nm foundry depends on. The announcement came alongside the topping-out of a €1.1 billion Dresden fab expansion at GlobalFoundries' site in Germany — a construction milestone the company described as a strategic anchor for European semiconductor supply chains.

The technology represents the first public commitment by any foundry to extend planar FD-SOI transistors into single-digit nanometer territory. Whether it delivers on that claim will depend on a manufacturing challenge GF has not yet solved, a government approval that has not yet been granted, and an EDA ecosystem that will not be ready until mid-2027 at the earliest.

One day before the FDX Fusion announcement, GF also signed a separate $2 billion TSMC interposer deal to produce silicon interposers for TSMC's CoWoS advanced packaging ecosystem at GF's Malta, New York facility — making GlobalFoundries a supplier inside the same AI packaging supply chain it is separately trying to serve at the edge. Volume production at Malta is expected in the first half of 2028.

What FD-SOI Is and Why It Runs Cool

To understand what GF is betting on, it helps to start with what FD-SOI actually does differently from the transistors inside every high-end smartphone and data-center GPU.

In a conventional FinFET — the three-dimensional transistor architecture used by TSMC, Samsung, and Intel at advanced nodes — the silicon channel that carries current stands up vertically like a fin, with the gate wrapping around three of its sides. This geometry improves electrical control of the channel but comes with two structural tradeoffs: it requires EUV lithography at sub-7nm nodes to define the fins reliably, and the three-dimensional structure makes it difficult to independently bias the transistor body — the bulk of silicon beneath the channel region.

FD-SOI takes a different approach. The transistor channel in GF's FDX platform sits in an approximately 70-angstrom silicon film placed above a buried silicon dioxide layer called the buried oxide, or BOX. Because this film is thin enough that the depleted region spans its entire thickness, no channel doping is required — which is where the "fully depleted" name comes from and why the architecture eliminates the random dopant fluctuation that causes leakage in scaled bulk CMOS. The buried oxide also electrically isolates the transistor channel from the bulk substrate beneath it, preventing substrate coupling at millimeter-wave radio frequencies — a structural advantage for automotive radar chips and sub-terahertz communications that FinFET cannot replicate without separate passive isolation structures.

The BOX's second function is the one that most distinguishes FD-SOI in power-sensitive applications: it creates a back-gate electrode. By applying a voltage to the bulk silicon beneath the BOX, designers can adjust the threshold voltage of the transistor at runtime — raising it to cut leakage when performance is not needed, or lowering it to boost switching speed when it is. This technique, called body biasing or adaptive body biasing (ABB), achieves approximately 85 millivolts per volt of bias in FD-SOI, compared to roughly 25 millivolts per volt in conventional bulk CMOS technology. That 3.4-to-1 advantage means a chip designer can squeeze performance out of the same transistor that would otherwise run at the power floor — or throttle power below what any static design could achieve.

The structure also permits what GF calls heterogeneous integration at the die level: the bulk silicon beneath the BOX can simultaneously host high-voltage power devices while the FD-SOI surface carries dense logic — a feature that matters for automotive chips managing both digital inference and power-conversion tasks.

What FDX Fusion Promises — and What It Does Not Specify

GlobalFoundries says FDX Fusion's first generation will deliver 7nm-class digital performance and more than double the transistor density of its existing 22FDX node. The platform is also designed to provide RF performance up to 0.5 THz fT/fMAX, analog and mixed-signal capability, in-memory computing, and embedded non-volatile memory on a single process technology. GF calls the integration concept for these capabilities STAC: Sense, Think, Act, Communicate — the signal chain of a Physical AI system.

Several questions the announcement does not answer deserve direct attention from engineers evaluating the platform.

First, GF does not disclose contacted gate pitch, minimum metal pitch, or cell density metrics for FDX Fusion — the technical specifications that independent analysts use to compare one node's density claims against another. The phrase "7nm-class digital performance" can mean switching speed, clock frequency at a given power, standard cell performance, or something else entirely. GF has not specified which benchmark it applies. That is a common practice in foundry marketing, but it means the density claim cannot currently be independently verified against TSMC N7 or Samsung 7nm, both of which publish pitch data. As independent analysis observed, the 7nm comparison describes claimed digital performance; the announcement does not make FDX Fusion a conventional 7nm manufacturing process.

Second, FDX Fusion appears to be engineered for deep ultraviolet (DUV) immersion lithography — GlobalFoundries does not operate EUV tools. Achieving true sub-10nm interconnect pitches using DUV requires multi-patterning, a technique in which the same layer is printed multiple times with different masks to achieve spacings finer than the light source can resolve in a single exposure. Whether multi-patterning on DUV can deliver the metal pitches needed to match the density and speed of established EUV-enabled 7nm nodes is a question GF's announcement does not answer — and the industry will be watching the 2027 demonstrator silicon closely for that answer.

Infineon, Tesla, and the Customer Roster

A set of marquee names endorsed FDX Fusion at announcement: BMW, Bosch, Infineon, NXP, Siemens, and Tesla all appeared in GF's press release, though the depth of each company's commitment varies significantly.

The most specific commitment came from Infineon. Patrick Press, Executive Vice President of External Wafer Manufacturing at Infineon, confirmed the companies are actively working together: "Together, Infineon and GlobalFoundries are strengthening their collaboration to define and explore future 7nm-class FDX Fusion technologies for next-generation radar and wireless communication products." Infineon's interest is explicable: for automotive radar chips operating at 77 GHz and above, the substrate isolation that FD-SOI provides is a direct performance advantage over competing bulk FinFET implementations.

Tesla's VP of Supply Chain, Karn Budhiraj, offered a broader endorsement: "The development and manufacturing of high-performance compute devices for edge processing is key to unlocking the next generation of advanced robotics and autonomous systems. GF's technology roadmap reflects the type of semiconductor investment needed to bring physical AI to the masses." Tesla's stake in advanced edge processors for robotics applications — including its Optimus humanoid robot program — gives the comment concrete strategic context.

Bosch's Dr. Axel Kaschner, Senior Vice President, Business Unit Integrated Circuits, Mobility Electronics, described FDX Fusion as "an important step towards delivering the semiconductor platforms needed to bring sensing, control, connectivity and efficient edge intelligence together for the next generation of robotics and automation."

NXP and Siemens each offered supportive statements without announcing specific product programs, and BMW expressed interest in supply chain resilience as much as the technology itself.

To support smaller design teams, GF also announced it would offer processor IP based on the MIPS, ARC, and RISC-V architectures — IP it has accumulated through acquisitions, including its August 2025 acquisition of MIPS and its pending acquisition of Synopsys' ARC Processor IP business, announced in January 2026 — reducing the barrier for fabless startups building specialized Physical AI SoCs.

The Dresden Condition

FDX Fusion's development path carries a qualifier that GF's press release states explicitly but that is easy to miss in a headline: "GF Dresden intends to pursue the technology's development through the upcoming IPCEI Advanced Semiconductor Technologies (AST) program, subject to German federal government approval."

IPCEI, the Important Projects of Common European Interest mechanism, is the state-aid framework under which the European Union authorizes member governments to subsidize R&D-intensive semiconductor projects. The SPRINT expansion project itself is already supported under this framework — funded by the EU through the European Chips Act, the German federal government, and the Free State of Saxony, with reports citing approximately €495 million from the European Chips Act portion. But the FDX Fusion technology development program requires a separate IPCEI AST approval that the German federal government has not yet granted.

The topping-out ceremony itself — the physical construction milestone celebrated on October 9 — applies to the SPRINT expansion, which is on schedule. The FDX Fusion R&D program attached to that facility is a separate commitment that depends on that federal decision.

CEA-Leti CEO Sébastien Dauvé, whose institution has collaborated with GF and Soitec on FD-SOI research for decades, expressed enthusiasm for the announcement: "We are delighted that GlobalFoundries has announced its next-generation 'single-digit FD-SOI' node, building on technology that CEA-Leti has been advancing for decades. Through the FAMES pilot line, CEA-Leti continues to shape the future European roadmap for FD-SOI and works every day to promote its adoption in a wide range of applications."

Soitec, which supplies the specialized SOI wafers that GF's FDX platform is built on, is also a development partner. Soitec's substrate technology — which uses a process called Smart Cut to produce ultra-thin silicon films bonded above a buried oxide layer — is what makes FD-SOI manufacturable at scale, and the FAMES pilot line connects that research substrate work to production-ready wafer supply.

The Ecosystem Question

Commercial success at any process node depends not just on the transistor architecture but on the surrounding design infrastructure: EDA tool support, certified standard-cell libraries, memory compilers, interface IP, and silicon-proven analog blocks. GlobalFoundries has not announced commitments from EDA vendors — Cadence, Synopsys, Siemens EDA — for FDX Fusion-specific PDK support. By contrast, 22FDX launched with certified flows from major EDA vendors and an interoperable PDK (iPDK) standard.

An initial FDX Fusion PDK is not planned until mid-2027. That timeline gives EDA vendors and IP providers roughly six months between the PDK release and any early customer chip starts — a compressed schedule for certifying the kind of production-grade design flows that large-volume customers such as automotive OEMs require.

The automotive and industrial partners already named in GF's announcement are sophisticated enough to bring their own IP for specific applications. Attracting the broader wave of fabless chip designers that would make FDX Fusion a high-volume node will require the same kind of certified, multi-vendor design ecosystem that 22FDX built over several years — and building it takes time regardless of how strong the underlying transistor technology is.

Inside the Bigger Picture: Two GF Bets in One Week

The FDX Fusion announcement arrived one day after GlobalFoundries disclosed its $2 billion TSMC deal for silicon interposers. The timing is notable: on October 8, GF positioned itself as a supplier inside TSMC's advanced AI packaging supply chain; on October 9, GF positioned itself as an independent platform provider for the edge-AI segment of the same market.

The two roles are not contradictory. Silicon interposers sit beneath AI processors and high-bandwidth memory in TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packages — they are precision substrates, not logic chips, and manufacturing them is an extension of GF's existing wafer fabrication capabilities rather than a claim to leading-edge logic competitiveness. GF's Malta, New York facility, which will produce the interposers, already operates a production-qualified 65PKG interposer platform. Large-scale production at Malta is expected to begin in the first half of 2028 — the same year FDX Fusion targets Dresden volume manufacturing.

For a foundry that exited the leading-edge process race in 2018 when it canceled its 7nm FinFET program, executing both programs on parallel 2028 timelines would mark a substantive repositioning. The TSMC deal validates GF as a packaging-tier partner for data-center AI. FDX Fusion, if it reaches production, would make GF a logic-tier partner for Physical AI at the edge. Neither role requires displacing TSMC or Samsung in leading-edge logic — and that is precisely the strategic design.

The real test will arrive in early 2027 when actual FDX Fusion demonstrator silicon reaches customer hands, and again in 2028 when yield data and cost structures become visible. GlobalFoundries is making a long-term argument that the next wave of AI semiconductor demand will be shaped by power efficiency, heterogeneous integration, and millimeter-wave RF capability rather than raw transistor density — and that FD-SOI, extended with the right architecture, is where that demand lands.

That argument is credible. Whether FDX Fusion can technically fulfill it remains, for now, an open question.

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Frequently Asked Questions

What is body biasing, and why does GlobalFoundries say it matters for Physical AI chips?

Body biasing (also called back-gate biasing or adaptive body biasing) is a technique unique to FD-SOI transistors that lets chip designers change a transistor's switching threshold at runtime by applying a voltage to the bulk silicon beneath the buried oxide layer. Raising the body bias increases the threshold voltage, cutting leakage power when peak performance is not needed. Lowering it reduces the threshold, boosting speed when it is. FD-SOI achieves roughly 85 millivolts of threshold shift per volt of body bias — about 3.4 times the effectiveness of body biasing in conventional bulk CMOS. For Physical AI applications like autonomous-vehicle sensor fusion or industrial robots, where the chip must run at low power most of the time but respond instantly to events, this dynamic control is a meaningful efficiency advantage that FinFET transistors cannot replicate.

When will FDX Fusion chips actually be available?

GlobalFoundries has set three forward milestones: demonstrator silicon for early customer evaluation is targeted for early 2027; an initial process design kit (PDK) is planned for mid-2027; and volume manufacturing in Dresden is planned for 2028. However, the development program in Dresden is explicitly conditioned on German federal government approval of an IPCEI Advanced Semiconductor Technologies funding program — an approval that has not yet been granted. If that approval is delayed or denied, the FDX Fusion timeline could shift.

Does GlobalFoundries use EUV lithography for FDX Fusion?

No. GlobalFoundries does not operate extreme-ultraviolet (EUV) lithography tools. FDX Fusion is engineered for deep ultraviolet (DUV) immersion lithography with multi-patterning — a technique in which layers are exposed multiple times with different masks to achieve finer feature sizes than DUV can print in a single step. Whether multi-patterning on DUV can deliver the interconnect pitches needed to match 7nm FinFET nodes in logic density is a technical question the announcement does not resolve and that demonstrator silicon in 2027 will begin to answer.

What is the significance of the simultaneous TSMC deal?

On October 8, 2026 — one day before the FDX Fusion announcement — GlobalFoundries signed a $2 billion, five-year agreement to manufacture silicon interposers for TSMC's CoWoS advanced packaging ecosystem at GF's Malta, New York facility. Interposers are the silicon substrates that sit beneath AI processors and high-bandwidth memory in high-performance computing packages. By simultaneously entering the AI packaging supply chain as a TSMC supplier (Malta) and announcing an independent edge-AI platform (FDX Fusion in Dresden), GF is positioning itself at two distinct points in the AI semiconductor value chain — without needing to compete with TSMC or Samsung in leading-edge logic.