SK Hynix president and chief development officer Ahn Hyun took the stage at Seoul's COEX convention center on Wednesday to deliver the most detailed next-generation memory roadmap the company has ever put before a public audience, formally disclosing a 3D Stacked DRAM architecture that bonds DRAM dies directly onto the processor die using Through-Silicon Via interconnects — eliminating the silicon interposer that current High Bandwidth Memory requires and targeting mass production in 2028.

Speaking at the 28th Korea Semiconductor Exhibition (SEDEX 2026), Ahn also advanced the company's High-Bandwidth Flash format, whose Open Compute Project technical specification is now finalized enough to target a complete standard in January 2027 with Google Tenstorrent HBF consortium already in place.

Memory Wall Moves: SK Hynix Maps New Hierarchy at SEDEX 2026

Ahn titled his address "Evolution Direction of Memory Technology in the AI Era" and opened it by recasting the standard memory bottleneck as structurally different from previous cycles. The original "memory wall" — the bandwidth gap between processors and DRAM that architects have managed since the 1990s — sat between compute and the first memory tier, he argued. The new one sits between the tiers of the memory hierarchy themselves, as AI workloads generate data volumes that cascade from on-chip SRAM through HBM and server DRAM all the way down into enterprise SSD storage.

To quantify why incremental HBM improvements cannot solve this problem, Ahn invoked the Jevons Paradox — the 19th-century economic observation by William Stanley Jevons that improvements in steam-engine coal efficiency produced greater total coal consumption, not less, because lower cost enabled wider use. Applied to AI, the argument runs: as models become more efficient, inference becomes cheaper, expanding access and increasing total token generation rather than reducing it. SK Hynix's own analysis of agentic AI — systems in which models communicate autonomously with one another — estimates that these agents consume between 25 and 100 times more tokens per task than a single human-directed session does.

The resulting aggregate demand projection is stark. SK Hynix projects that AI infrastructure performance requirements will grow 19 to 20 times by 2030, compounding three forces: reasoning chains growing in complexity, context windows expanding, and simultaneous request volumes climbing. As a worked illustration, Ahn said running 1,000 concurrent one-million-token sessions already generates about 13 terabytes of inter-tier data movement—a footprint that exceeds what HBM and server DRAM can hold, forcing spillover into far slower SSD storage.

How Does 3D Stacked DRAM Differ from HBM?

Current HBM packages multiple DRAM dies in a vertical stack and places that stack beside the processor on a flat silicon interposer — what the industry calls 2.5D integration, per HBM's 2.5D interposer design. Data travels from the processor across the interposer to the memory stack laterally, through a wide parallel bus that today runs at up to 1,024 bits wide. That lateral routing is both the source of HBM's bandwidth advantage over standard DDR5 and, increasingly, the limiting factor in how far that advantage can be extended: the interposer imposes a practical ceiling on how many I/O connections can be made per unit of package area.

SK Hynix's 3D Stacked DRAM eliminates the lateral interposer entirely. In its architecture, DRAM dies bond directly atop processor dies—a GPU, NPU, or AI accelerator—using Through-Silicon Via interconnects: vertical copper pillars that pass through each die's silicon body and connect to the next die above it. Because the DRAM sits above the processor rather than beside it, data travels vertically through the silicon stack rather than horizontally through package routing. The density of available connections between processor and memory expands by orders of magnitude compared to an interposer-based approach, and the average data-travel distance shrinks to the thickness of a few silicon dies rather than millimeters of interposer trace.

Ahn described this configuration as enabling far higher bandwidth and lower power per bit claimed, compared to any 2.5D interposer-based design. SK Hynix is targeting mass production in 2028, and is developing a 16-active-die configuration. At SEDEX, Samsung's competing zHBM architecture — which also places memory directly on top of AI chips — was framed as the closest competitive reference point; SK Hynix's announcement positions its own processor-integrated DRAM as the targeted production architecture rather than a research concept.

Why 3D Stacked DRAM Makes Memory a Co-Designed Component

The technical description of 3D Stacked DRAM understates the architecture's biggest structural implication: if DRAM is bonded directly onto a GPU or NPU die, memory is no longer an interchangeable commodity that chip designers select from a catalog. It becomes a co-designed component that must be specified, validated, and fabricated in partnership with the chip designer years before product launch.

Current HBM, despite being complex, connects to processors through a standardized interposer interface. A chip designer can swap in HBM4E from SK Hynix, Samsung, or Micron without redesigning the processor. 3D Stacked DRAM breaks that fungibility. The processor die must be designed with the DRAM mounting area predefined, its power delivery and thermal dissipation engineered around the DRAM stack's heat load, and its backend-of-line processing coordinated with the memory maker's bonding process. That level of integration requires the GPU or NPU maker to share proprietary process information with SK Hynix — and to commit to a specific memory partner — well before tape-out.

This is why Ahn's SEDEX closing call for South Korea's chipless designers, materials suppliers, and global partners to create a new AI ecosystem in Korea was not rhetorical. 3D Stacked DRAM cannot be built and sold the way HBM is sold; it requires an ecosystem of co-design partnerships that does not yet exist at scale, and SK Hynix's 2028 production target partly depends on how long it takes to establish those partnerships. Ahn drew on the 1960s Apollo program as his analogy for the required coordination, noting the role the program played in catalyzing the U.S. semiconductor industry.

High-Bandwidth Flash: NAND Gets TSV Stacking for AI Inference

Between the HBM tier and conventional enterprise SSDs, SK Hynix is inserting an entirely new category. High-Bandwidth Flash (HBF) takes the TSV stacking and high-speed packaging processes developed for HBM and applies them to NAND flash memory dies rather than DRAM. The result is a fundamentally different performance-and-capacity point: Ahn stated that HBF delivers half HBM bandwidth and ten times the capacity.

That tradeoff is deliberate and workload-specific. HBF is not designed to replace HBM for AI training, where matrix multiplication operations demand the lowest possible memory latency and the full bandwidth of an HBM stack. It is designed for AI inference, where a fixed model's weights and the session's KV-cache data are read repeatedly — while write operations account for a negligible fraction of total memory traffic. That read-dominated pattern plays directly to NAND's strengths (fast reads at low power) while sidestepping its well-known limitations (slower writes, finite write endurance).

Ahn also pointed to prefetch techniques as a mechanism to narrow the effective performance gap with DRAM. By predicting and preloading data before it is explicitly requested — an established technique in both processor cache hierarchies and SSD controllers — HBF can prefetch to mask NAND latency at the system level, making its effective bandwidth available to the application sooner than raw NAND read-latency specifications would suggest.

SK Hynix's own simulation of its H³ architecture — a hybrid configuration that places HBM and HBF on a single interposer beside the GPU — showed 2.69 times the throughput per watt of an HBM-only configuration, according to research the company published at FMS 2026.

OCP Specification Targets January 2027; Google Already in Consortium

SK Hynix is not building HBF in isolation. The company disclosed that it began joint research with SanDisk on the format in early 2025 and that the two companies published a formal standardization partnership in February 2026. In August 2026, at the Future of Memory and Storage (FMS) conference, they published version 0.7 of an OCP technical specification for HBF.

That specification defines 8-high 16-high NAND die stacks with capacities up to 512 gigabytes and three bandwidth grades spanning approximately 0.4 terabytes per second to 3.0 terabytes per second, with processor connectivity via UCIe, the open chiplet interconnect standard developed by Intel, AMD, ARM, TSMC, Samsung, and others.

UCIe's role as the interface matters because it means any processor that implements the UCIe standard—regardless of manufacturer—can host HBF without a custom proprietary connection, a deliberate design choice that prioritizes ecosystem breadth over tight integration. The UCIe Consortium's version 3.0, released in August 2025, runs at 64 gigatransfers per second.

Major cloud operators are already engaged. Google participated in the HBF panel discussion at FMS alongside SK Hynix and SanDisk, and Tenstorrent is also confirmed as a consortium member. SK Hynix is targeting finalization of the complete standard in January 2027, after which the industry can converge on a common interface for the new tier. SEDEX confirmed CSPs are co-developing the architecture, suggesting that beyond Google, additional hyperscalers have participated in specification development without being publicly named yet.

Custom HBM, CXL Pooling, Storage-Next: SK Hynix's Parallel Roadmap Tracks

The SEDEX keynote also covered three additional development tracks running in parallel with 3D Stacked DRAM and HBF.

Custom HBM is positioned as an expanding revenue and differentiation lever as SK Hynix's product line advances from HBM4E toward HBM5. Rather than selling a monolithic standardized product to all customers, SK Hynix is embedding custom HBM base die functions directly into the HBM base die, allowing major hyperscalers or accelerator vendors to receive variants tailored to their specific AI architectures. The company shipped samples of HBM4E — 12 layers, running at 16 gigabits per second with a 20-percent efficiency gain over HBM4 — in June 2026.

CXL-based Pooled Memory addresses the inefficiency that emerges when multiple GPUs within a data center simultaneously hold idle DRAM capacity. By connecting server memory banks over a CXL fabric, SK Hynix's design lets GPU clusters dynamically share underutilized DRAM across cards, improving aggregate utilization without requiring each GPU to carry its worst-case peak memory allocation.

Storage-Next is SK Hynix's project, co-developed with several unnamed major technology companies, for a next-generation enterprise SSD with an internally redesigned controller. The company states that concept design is complete and active development is underway, targeting four to eight times IOPS of current-generation enterprise SSD products. Storage-Next is positioned as the anchor of the lowest tier in the restructured hierarchy, providing the high-throughput persistent storage that feeds data upward through HBF, HBM, and eventually on-chip SRAM as AI inference pipelines process it.

Taken together, the SEDEX roadmap describes a full restructuring of the AI memory hierarchy: on-chip SRAM → 3D Stacked DRAM → HBM → HBF → Server DRAM → Storage-Next SSD — each tier distinguished by a specific bandwidth-to-capacity tradeoff matched to a specific workload characteristic.

Frequently Asked Questions

What is 3D Stacked DRAM and how does it differ from HBM?

3D Stacked DRAM bonds DRAM dies directly on top of a logic die — a GPU or AI accelerator — using Through-Silicon Via (TSV) interconnects, which are vertical copper pillars through the silicon body. High Bandwidth Memory (HBM) also uses TSV interconnects between DRAM dies within its stack, but the stack itself sits beside the processor on a flat silicon interposer (2.5D integration) and connects to the processor laterally.

3D Stacked DRAM eliminates that interposer entirely, shortening data paths to the thickness of a few silicon dies and dramatically increasing the density of available connections between processor and memory. The tradeoff is that 3D Stacked DRAM requires deep co-design between the memory maker and the chip designer — memory can no longer be treated as an interchangeable commodity plugged in at the package level. SK Hynix is targeting mass production in 2028.

When will High-Bandwidth Flash (HBF) be available, and what is the OCP specification?

HBF does not yet have a commercial production date, but its Open Compute Project technical specification is on track. Version 0.7 was published at the Future of Memory and Storage (FMS) conference in August 2026, defining 8-high and 16-high NAND die stacks with capacities up to 512 gigabytes, bandwidth grades from 0.4 to 3.0 terabytes per second, and a UCIe chiplet interconnect interface.

SK Hynix and SanDisk are co-developing the format, with Google and Tenstorrent among confirmed ecosystem participants. The full specification is targeted for January 2027, after which chip designers can implement the UCIe interface on new processors and expect HBF compatibility.

Why does AI inference need a separate memory tier like HBF, and why can't HBM alone serve it?

AI inference requires holding very large amounts of data — model weights, which can run into hundreds of gigabytes, and KV-cache records for ongoing sessions — that must be read repeatedly but rarely written. HBM delivers exceptional read bandwidth but is expensive per gigabyte and limited in total capacity per accelerator. HBF addresses this by delivering roughly ten times more capacity than an equivalent HBM configuration, at roughly half the bandwidth, using NAND flash dies packaged in the same TSV stack format as HBM.

For workloads where you need to store enormous amounts of data that is read but seldom written — which describes large-scale inference almost exactly — HBF's capacity advantage outweighs its bandwidth gap, especially when prefetch techniques are used to mask NAND's inherent read latency.

Does SK Hynix's 3D Stacked DRAM roadmap make HBM obsolete?

No. SK Hynix's SEDEX roadmap explicitly positions HBM, 3D Stacked DRAM, and HBF as distinct tiers serving distinct purposes, not as sequential replacements. HBM is optimized for latency-sensitive matrix math in AI training and hot-path data in inference—it will remain in the hierarchy. 3D Stacked DRAM targets the bandwidth density gap between on-chip SRAM (extremely fast, tiny capacity) and HBM (fast, but constrained by the interposer interface), offering a tier with even higher bandwidth than HBM for the most latency-critical data.

HBF targets the capacity gap between HBM and server DRAM for read-dominated inference data. The result is a six-tier hierarchy—SRAM, 3D Stacked DRAM, HBM, HBF, Server DRAM, and Storage-Next SSD—where each tier exists because the tier above it cannot cost-effectively serve the data volumes below it.