At the Open Compute Project Global Summit on Monday, Cisco turned a multi-year silicon roadmap into a production reality: its 102.4 Tbps Silicon One G300 switching chip is now in customers' hands, shipping inside new N9000 and Cisco 8000 series systems. The same announcement unveiled the Silicon One G302 — a new 51.2 Tbps top-of-rack switching chip the company had not previously telegraphed — and formalized a joint effort with NVIDIA to develop the Ultra-Dense Small Form Factor Pluggable (USFP), a new optics standard rated at 400 Gb/s per lane.

What those three announcements add up to is something the surface-level product news underplays: Silicon One is now competing for the same class of hyperscaler design wins that Broadcom has long treated as a captive market — and Alibaba's in-house Quantum Cat router, a customer-designed chassis running on Cisco silicon with SONiC as its operating system, is the clearest evidence that the merchant-silicon model Broadcom built can be replicated.

OCP 2026 runs through Wednesday at the San Jose McEnery Convention Center; the OCP Global Summit agenda lists keynote speakers from AMD, Arm, Broadcom, Google, Intel, Meta, Microsoft, NVIDIA, and Oracle. The conference is expected to attract 7,000 to 9,000 attendees over its four-day run.

G300 Crosses from Roadmap to Production

Cisco first unveiled the Silicon One G300 at Cisco Live EMEA on February 10, 2026. As of OCP 2026, the chip has cleared its next milestone: customer sampling is open, and G300 systems are shipping inside Cisco N9000 and 8000 series platforms. The G300 powers a new generation of fixed and modular Cisco N9000 and Cisco 8000 systems, available in both liquid-cooled and air-cooled configurations.

Cisco claims the G300 delivers a 28% improvement in AI training job completion time by enabling sustained GPU utilization at scale. That figure requires context: it is vendor-stated and derived from Cisco's internal simulation and benchmarking methodology, not an independently verified head-to-head evaluation against production hardware.

Independent benchmarking of AI networking silicon at hyperscale is methodologically difficult and slow to surface publicly; the claim is plausible given how the G300's architecture addresses documented congestion failure modes in GPU clusters, but production validation by hyperscale operators running real training workloads will ultimately settle it.

The G300 also supports post-deployment programmability via the P4 packet-processing language. Network operators can update the chip's forwarding behavior in the field without replacing hardware—a genuine architectural distinction from conventional merchant silicon, where functionality is fixed at tape-out, and changes require a silicon refresh cycle.

How Silicon One G300's Network Architecture Actually Works

Understanding what the G300 does differently requires understanding how AI training networks fail at scale. In large GPU clusters, hundreds or thousands of accelerators synchronize gradient updates during the backward pass. When multiple flows collide on the same egress link, conventional Equal-Cost Multi-Path (ECMP) load balancing — which hashes flows to network links deterministically — cannot redistribute in-flight traffic; the result is congestion on some links while others sit underutilized, and congested links force GPUs to stall waiting for network acknowledgment rather than computing.

Cisco's response is what it calls Intelligent Collective Networking (ICN). ICN combines three mechanisms. First, a fully shared 252-megabyte packet buffer — the largest per-chip in any switching ASIC at this bandwidth tier — allows the G300 to absorb large traffic bursts without dropping packets. Second, path-based load balancing: rather than pinning a flow to a single link for its entire duration, ICN can reroute individual packets based on real-time link conditions, treating flows as collections of paths. Third, a global congestion map: in a multi-G300 fabric, each chip shares its congestion state with its neighbors in real time via the Silicon One ICN fabric, enabling load-balancing decisions that reflect the state of the entire cluster rather than a single hop.

The combined result is a fabric designed to keep GPUs computing rather than stalling on network acknowledgment. Whether the 28% job completion time claim holds across real customer workloads is an empirical question — but the architectural logic connecting the ICN design to that performance outcome is sound, and it is the specific technical reason Cisco can credibly claim differentiation from a conventional ECMP-based merchant switching fabric.

G302: Top-of-Rack Silicon Built for Liquid-Cooled AI Racks

Cisco's more surprising announcement at OCP was the Silicon One G302, a chip the company had not telegraphed ahead of the conference. The G302 is a 51.2 Tbps switching ASIC with 200G SerDes, designed specifically for top-of-rack (ToR) deployment in GPU-dense AI server racks, as detailed in the Cisco OCP 2026 announcement.

The 200G SerDes figure matters at the rack level because it enables 1.6 Tbps optical connectivity per host port: each G302 can support host-side breakout at 1.6 Tbps per server, aggregating the full bandwidth of next-generation accelerator interconnects before forwarding traffic to higher-tier spine switches. Cisco has paired this with native direct-to-chip liquid cooling as part of the G302's system integration specification — not as an optional accessory but as a standard element — reflecting a shift underway across the data center: at modern GPU rack power densities, switching silicon placed in close proximity to accelerators operates in an environment where air cooling is increasingly insufficient, and hyperscalers are demanding that networking components be co-designed with thermal infrastructure rather than retrofitted.

Cisco has committed the G302 to OCP's ESUN (Ethernet Scale-Up Network) working group, signaling that its ToR role is designed to fit within a broader standards-aligned scale-up architecture rather than a proprietary silo. The G302 carries a year-end 2026 shipping commitment.

USFP: Cisco and NVIDIA Bet Against Co-Packaged Optics

The longest-horizon announcement from Cisco's OCP 2026 press release is the USFP specification. Together with NVIDIA, Cisco unveiled plans to jointly develop the Ultra-Dense Small Form Factor Pluggable: a new optical module class rated at 400 Gb/s per lane, compared with the 200 Gb/s per lane that currently represents the leading edge of high-density pluggable optics.

Cisco and NVIDIA are targeting four times the bandwidth density of current high-density pluggable modules and 1.3 times the power efficiency. If achieved in production hardware, those figures would make USFP competitive with co-packaged optics on the two dimensions that make CPO attractive to hyperscalers.

The strategic logic of USFP is a bet that CPO-like performance can be reached without sacrificing field replaceability. Co-packaged optics integrates the optical transceiver directly onto the switch ASIC substrate, eliminating the optical connectors responsible for signal loss and power overhead in conventional pluggable designs. CPO theoretically delivers superior density and power per bit — but when a CPO-integrated transceiver fails, the affected switch must be returned for depot-level repair rather than swapped in the field by a technician.

Data center operators have built their maintenance workflows around pluggable optics: hot-swappable, field-replaceable, tested and stocked independently of the underlying switching silicon. USFP is designed to close the performance gap while preserving that operational model.

To drive broad industry adoption, Cisco and NVIDIA plan to create an open multi-source agreement (MSA) community for USFP. MSA processes at this scope typically require 12 to 18 months from initial drafting to a ratified final specification, with broad vendor sampling and production hardware following after ratification. Without participation from transceiver manufacturers, system vendors, and hyperscalers, any new form factor risks being perceived as a two-vendor proprietary standard rather than an ecosystem anchor.

Microsoft and Alibaba Deploy P200: What Their Production Choices Reveal

Cisco's hyperscaler endorsements at OCP 2026 center on the Silicon One P200 routing silicon introduced at OCP 2025, now running in production at two of the world's largest cloud operators. The distinction between routing and switching silicon is deliberate: the P200 is a scale-across chip designed for backbone and data center interconnect workloads, not the same market as the G300's spine-class switching role.

Microsoft has moved its P200-based systems into production for cloud and high-performance services. Anand Ramakrishna, Corporate Vice President of Engineering at Microsoft, cited P200 buffering architecture as the specific technical capability enabling Microsoft's cloud workloads. The Microsoft deployment is a significant production data point, but the Alibaba Cloud announcement carries the more strategically consequential implication.

Alibaba Cloud has deployed its next-generation backbone network — called eCORE — at massive scale, using Alibaba's own Quantum Cat router powered by Silicon One P200. The Quantum Cat is an Alibaba-designed chassis, not a Cisco system. It runs SONiC — the open-source network operating system originated at Microsoft and now maintained through the Linux Foundation SONiC Project — not Cisco's own NX-OS or IOS XR. Dennis Cai, VP and Head of Network Infrastructure at Alibaba Cloud Intelligence Group, described the combination as proof of open networking's value in delivering flexibility for demanding workloads.

Stated plainly: Alibaba built its own router, put Cisco silicon inside it, ran community-maintained open-source software on top, and deployed the result at backbone scale. This is exactly the merchant-silicon model Broadcom built with Tomahawk — hyperscalers and whitebox OEMs buy the silicon; they design their own systems, choose their own software stacks, and own the resulting network architecture. When Cisco launched Silicon One in 2019, it explicitly promised to sell silicon into customer-designed platforms. The Alibaba eCORE deployment is the most public evidence to date that the promise has been kept.

Can Silicon One Compete With Broadcom for Hyperscaler Design Wins?

OCP 2026 poses a direct competitive question: whether Cisco has built the organizational and ecosystem infrastructure to win design-win competitions that Broadcom's Tomahawk 6 switching ASIC — a 102.4 Tbps, TSMC 3nm chip — has historically dominated. The Tomahawk 6 is a direct bandwidth-tier competitor to the G300: both chips deliver 102.4 Tbps with 512 SerDes lanes at 200G, and both are manufactured on TSMC's 3nm process. Cisco's claim of architectural differentiation through ICN's shared buffer and global congestion map must be weighed against Broadcom's SDK maturity, its years of accumulated hyperscale integration work, and the operational familiarity that incumbent silicon commands.

NVIDIA's Spectrum-X is a third competitor targeting GPU-to-GPU scale-up workloads — the high-speed intra-cluster fabric used during training — where tight NIC-to-switch co-design and InfiniBand-style flow control have produced measurable performance advantages, according to Spectrum-X published performance evaluations. Both the G300 and the G302 target segments where Spectrum-X is gaining traction among AI infrastructure operators.

The USFP collaboration with NVIDIA is therefore layered: in optics, the two companies are jointly developing a shared standard; in switching silicon, they are competing for the same AI networking dollar. Co-opetition of this kind is increasingly common at the AI infrastructure layer — no single vendor can deliver every component of a hyperscale AI fabric at the required quality and price, so standardizing shared infrastructure components is often economically rational even between direct competitors. Data center operators who resist vertical lock-in actively prefer it: open standards create supplier optionality, and supplier optionality compresses margins across the ecosystem, which is exactly what hyperscale operators want.

What Comes Next

Cisco's OCP 2026 announcements sketch a roadmap with near-term and longer-horizon milestones. G300 systems are shipping now; the benchmark through the first half of 2027 will be how quickly hyperscalers beyond the initial design partners adopt it at volume and whether independent performance evaluations corroborate the vendor-stated ICN claims. The G302 carries a year-end 2026 shipping commitment; its liquid-cooling integration and 200G SerDes will face real-world validation as OCP ORV3 rack deployments accelerate across the industry. The USFP specification is the longest fuse in the set: MSA processes of this scope typically require 12 to 18 months from initial drafting to ratification, making broad vendor sampling unlikely before late 2027 at the earliest.

Beyond silicon and optics, Cisco used OCP 2026 to reinforce its open-software credentials. Its Nexus One SONiC deployment architecture provides a validated deployment path for multi-site to rack-scale environments. Cisco also announced Live Protect runtime security, a capability for SONiC customers planned for mid-2027, designed to reduce the exposure window between a vulnerability disclosure and a patch deployment. On the management plane, the Cisco 8001 — powered by the Silicon One A100 chip, in 10G or 1G configurations — allows operators to apply the same APIs and automation tooling used in production networks to out-of-band management, eliminating the need for a separate management environment.

Kevin Wollenweber, SVP and General Manager of Data Center and Internet Infrastructure at Cisco, framed Cisco's OCP positioning in terms that capture both the ambition and the challenge: "AI is redefining what it means to scale infrastructure. It's no longer just about individual data centers or clusters, but how we connect compute at massive scale without compromising performance or resilience. Cisco's strength across silicon, networking, optics, systems and security puts us in a unique position to deliver the open infrastructure customers need as AI continues to evolve."

The AI infrastructure market is projected to reach $600 billion in the coming years. For Cisco, the network-as-AI-differentiator thesis dates to Silicon One's 2019 launch. The Microsoft and Alibaba production deployments, the G300 now shipping, and the G302 on a year-end schedule represent the empirical evidence that the thesis has survived contact with reality. Whether it survives the competitive tests of 2027 — when Broadcom Tomahawk 6's ecosystem integration work will have matured, and hyperscalers making G300 volume decisions will simultaneously be designing their next-generation deployments — is a different question. That answer will not come from an OCP press release.

Frequently Asked Questions

What is the difference between the Cisco Silicon One G300 and G302?

The G300 is a spine-class switching chip at 102.4 Tbps, built for the large, high-tier switching fabrics that interconnect AI GPU clusters across many racks. The G302 is a top-of-rack chip at 51.2 Tbps — one tier lower in the network stack, aggregating traffic from individual servers inside a rack before forwarding it up to spine switches. The G302 adds 200G SerDes (enabling 1.6 Tbps optical connections to host servers) and integrates native direct-to-chip liquid cooling as a standard design element, making it purpose-built for the power-dense GPU rack environments where air cooling is no longer sufficient for networking hardware placed near accelerators.

What does Alibaba's eCORE deployment reveal about Cisco's competitive position in AI networking?

Alibaba's eCORE backbone uses a router Alibaba designed in-house — the Quantum Cat — powered by Cisco's Silicon One P200 and running SONiC, an open-source operating system unaffiliated with Cisco's own software stack. This is the merchant-silicon model in action: the customer owns the platform design, chooses its own software, and sources silicon as a commodity input. It is structurally equivalent to the design-win model that built Broadcom's Tomahawk franchise — the most significant evidence to date that Silicon One can compete for that class of hyperscaler engagement, not as a Cisco platform sale, but as a merchant-silicon design win.

How does USFP compare with co-packaged optics, and when can the industry expect production hardware?

USFP targets the same density and power-efficiency improvements that make co-packaged optics attractive — four times the bandwidth density of current high-density pluggable modules and 1.3 times the power efficiency — while preserving field replaceability. Co-packaged optics integrates the transceiver directly onto the switch ASIC, improving power per bit but requiring depot-level repair when a transceiver fails rather than a field swap. USFP is designed to avoid that operational constraint. The specification is in early stages: the open MSA community Cisco and NVIDIA are forming typically requires 12 to 18 months from drafting to a ratified final spec, with production hardware following after ratification. Broad availability of USFP-based products is unlikely before late 2027 at the earliest.

Has Cisco's claimed 28% AI training performance improvement for the G300 been independently verified?

No. The 28% improvement in AI training job completion time is a vendor-stated figure based on Cisco's internal simulation and benchmarking methodology. The claim has not been independently reproduced by a third-party evaluator. The architectural basis for the claim—that ICN's 252-megabyte shared buffer, path-based load balancing, and cross-fabric congestion map reduce GPU stalls caused by network congestion—is technically coherent, but translating that architectural advantage into a specific percentage improvement depends on workload characteristics that vary across deployments. Independent benchmarks from production operators running real training workloads will matter, and that data is not yet publicly available.