Intel headquarters is seen on July 23, 2026 in Santa Clara, California. Heather Diehl/Getty Images

A fresh analysis from ZDNet Korea, published September 11, 2026, documents a split that has been quietly forming for two years in the AI chip supply chain: the world's largest AI accelerators are no longer all going to the same packaging technology. Nvidia's flagship training processors continue to rely on TSMC's CoWoS. But Google, Amazon, Cisco, SpaceX, and Tesla have all committed to Intel's Embedded Multi-die Interconnect Bridge — the technology known as EMIB — for their inference-class chips and custom AI processors. That divergence is not a capacity accident. It is a workload verdict, and the underlying geometry explains exactly why each technology won the work it won.

The question of which packaging technology an AI chip uses was, until recently, barely a question at all. TSMC's CoWoS was the only viable option at scale, and getting a CoWoS allocation was itself the competitive barrier. As of this writing, CoWoS lead times still stretch 52 to 78 weeks for customers not named Nvidia, and TSMC's capacity remains sold out through 2026 and well into 2027. But the way companies are responding to that scarcity has changed. Rather than queuing indefinitely for CoWoS, Google, Amazon, and other hyperscaler ASIC teams have looked at what their chips actually need — and found that Intel's approach fits many of those needs more naturally, at lower cost, and at package sizes that CoWoS cannot efficiently serve.

To understand why the packaging market is splitting, it helps to understand what the two major AI workload categories actually demand from the package sitting around their chips.

Why Training and Inference Pack Differently

Training accelerators — the class Nvidia's Blackwell and Rubin GPUs belong to — run matrix multiply operations continuously at enormous scale, cycling data between compute units and high-bandwidth memory at rates measured in terabytes per second. Every additional nanosecond of memory latency compounds across billions of operations per second. For this workload, CoWoS's full silicon interposer is not overkill. It is purpose-built: the interposer spans the entire package floor with thousands of copper-filled through-silicon vias, providing the densest possible electrical connections between the GPU logic die and the stacked high-bandwidth memory modules beside it. The interconnect density is extraordinary — and that density has a cost in materials, a cost in manufacturing complexity, and a cost in geometry that grows with every generation of larger chips.

Inference accelerators and hyperscaler custom chips — the class Google's Tensor Processing Units, Amazon's Trainium, and MediaTek's AI ASICs belong to — have different requirements. They need more memory stacks and more compute dies in a single package to handle the parallelism of production AI inference workloads, which run many simultaneous requests rather than one enormous training job. The package needs to be larger, not necessarily denser at the die-to-die level. And they need more of them — Google's 2028 TPU order from Intel reportedly covers more than three million units. At those volumes and at those package sizes, the cost and geometry of CoWoS become the problem.

EMIB Architecture: What the Bridge Replaces

Intel's EMIB embeds small silicon bridges directly into the organic package substrate — only at the specific points where adjacent dies need to exchange data at high speed. The rest of the substrate is ordinary organic material. There is no silicon layer spanning the entire package floor. There is no redistribution layer interposer that must be built separately, diced, and bonded to the substrate as a second piece.

That elimination has three concrete consequences. First, it removes a layer of assembly complexity: the standard CoWoS process bonds a package in two steps (attach the interposer to the substrate, then attach the dies to the interposer), while EMIB bonds dies directly to the substrate in a single step. Second, it removes the primary cost driver: the full silicon interposer in CoWoS represents 40 to 60 percent package cost of the total, according to industry analysis. EMIB eliminates that component, which Intel claims produces a roughly 50 percent cost reduction versus CoWoS-L or CoWoS-R at equivalent package sizes. Third, and most consequentially for the current generation of AI chips, it removes the round-wafer geometry constraint that sets a ceiling on how large CoWoS packages can grow before the cost model collapses.

Why EMIB's Cost Advantage Compounds With Package Size

This geometry point is the largest implication the standard coverage of EMIB versus CoWoS typically misses, and it matters increasingly as AI chip packages grow larger with every generation.

CoWoS interposers are manufactured on standard 300mm (11.8-inch) round wafers. A round wafer cannot efficiently yield rectangular packages. At the sizes AI accelerators now demand — packages approaching and exceeding 5.5 times the photolithography reticle limit, or roughly 4,700 square millimeters (7.3 square inches) — a single 300mm wafer can produce only one or two interposers. The geometric waste at the circular edges of the wafer means that a round-wafer interposer process runs at roughly 60 percent substrate utilization. The IO Fund's packaging analysis from July 2026 documents this geometric constraint in detail.

Intel's EMIB bridges live inside the organic package substrate, which comes in rectangular panels — current formats run roughly 510mm by 515mm (20 by 20.3 inches). Rectangular panels pack rectangular packages without geometric waste. Panel utilization for EMIB approaches 90 percent. As packages get larger with every generation of AI chips, CoWoS's round-wafer utilization problem gets geometrically worse, while EMIB's rectangular-panel advantage scales in the same direction. The cost gap between the two approaches is not fixed; it widens with every generation of chips that demands a larger package. That is the structural mechanism behind EMIB's 50 percent cost claim, and it is why that claim does not shrink as AI chip complexity grows.

TSMC's current CoWoS-L variant — the version powering Nvidia's Blackwell and Rubin accelerators — already recognized this problem by replacing the monolithic silicon interposer with a hybrid design: an organic redistribution layer carrier with small "local silicon interconnect" bridges embedded only where die-to-die connections require silicon-level density. CoWoS-L today scales to 5.5 times the reticle limit (approximately 4,720 square millimeters, or 7.3 square inches), with a roadmap to 9.5 times reticle limit (approximately 8,150 square millimeters, or 12.6 square inches) in 2027. But the redistribution layer itself is still built on a round 300mm wafer, which means the geometry problem persists. At 9.5 times the reticle size, a single round wafer yields very few interposers.

Intel's EMIB-T already supports packages exceeding 8 times the reticle limit (approximately 6,860 square millimeters, or 10.6 square inches) — ahead of TSMC's current ceiling — and has a roadmap to packages exceeding 12 times reticle scale (more than 120mm by 180mm, or 4.7 by 7.1 inches) by 2028, accommodating 24 or more HBM stacks and 38 or more EMIB-T bridge connections. EMIB-T adds through-silicon vias through the embedded bridges themselves for vertical power delivery — enabling multi-kilowatt package power budgets that next-generation AI chips will require.

The Yield Milestone That Unlocked the Customer Pipeline

For most of the period since TSMC's CoWoS capacity crunch became severe in 2023, Intel's EMIB was a credible alternative in principle but not yet proven in production at the volume and yield levels that hyperscale customers require. That changed in mid-July 2026, when supply-chain checks by KeyBanc Capital Markets indicated that EMIB-T's yield had reached approximately 98 percent — up from roughly 90 percent just weeks earlier, which analyst Ming-Chi Kuo had characterized in May 2026 as a positive but still insufficient data point for mass production readiness. Reporting on Intel's broader yield improvements is documented in a prior TechTimes analysis of Intel Foundry's yield progress.

The 98 percent milestone matters because it is the mass-production yield standard required to make EMIB-T commercially viable at hyperscale volume. Packaged AI chips are among the most expensive components in the supply chain, combining high-value logic dies with multiple high-bandwidth memory stacks. A failed package is not just a wasted substrate — it is the loss of all the expensive components inside it. Yield above 98 percent means that number is bounded and manageable. That milestone arrived barely two weeks before The Information reported TSMC's own quasi-EMIB program with Kinsus Interconnect Technology, a sequencing that suggests a direct causal relationship: as EMIB-T achieved commercial yield parity with CoWoS, the argument for switching from CoWoS became substantially harder for customers to ignore — and TSMC's engineering response became substantially more urgent.

What Hyperscalers Are Actually Ordering

The customer list for Intel's EMIB platform has grown substantially since the first public commitments. Google is adopting EMIB-T packaging for its ninth-generation Tensor Processing Unit, codenamed "Humufish," targeting production in the second half of 2027, with an order reportedly covering more than three million units for 2028. Amazon's Trainium 3 accelerator is also reported to be targeting Intel's EMIB-T platform. Cisco and SpaceX are confirmed as external Intel Foundry customers. MediaTek announced in May 2026 that it would adopt a dual packaging strategy — using TSMC CoWoS for training-focused AI chips while deploying Intel EMIB for inference variants where package size requirements exceed what CoWoS can currently serve at competitive cost.

Intel CFO David Zinsner revised the external advanced-packaging revenue outlook upward over consecutive earnings calls — from "a few hundred million dollars" to revenues that could reach "several billion dollars per customer" for larger engagements. For comparison, Intel Foundry's total external foundry revenue was Intel Foundry's $293 million Q2 figure in the second quarter of 2026, making EMIB the most plausible near-term vector for meaningful foundry growth.

The customer profile is telling. Every major EMIB commitment involves either a custom ASIC — a processor designed to handle a specific workload at scale — or an inference-class chip that needs to integrate many more memory stacks in a larger package. None of Nvidia's flagship training GPU business has shifted to EMIB. The split is not incidental; it maps directly to the workload requirements and the geometry tradeoffs described above.

Where Does the Bandwidth Question Argument Stand?

EMIB's architectural approach — bridges only where dies connect, organic substrate elsewhere — means the interconnect density between dies is necessarily more localized than a full silicon interposer. The bridges provide exceptional bandwidth at the specific die-to-die and die-to-HBM interfaces they span, but there is no silicon highway across the entire package floor routing signals in every direction simultaneously. For the highest-bandwidth training workloads — where the matrix multiply throughput of an Nvidia H100-class GPU requires terabyte-per-second data movement in many directions simultaneously — CoWoS's full interposer delivers performance that EMIB's localized bridge approach cannot directly match. The inference workload shift toward EMIB reflects exactly this structural difference in what each packaging architecture is optimized to serve.

Citi analysts concluded in a mid-2026 research note that TSMC faces minimal near-term competitive pressure from EMIB-T on its highest-bandwidth customer segment, citing TSMC's mature ecosystem and deep integration with leading-edge process nodes. Nvidia's Blackwell and Rubin GPU lines continue to use CoWoS-L, and there is no indication that the flagship training-class GPU segment is rerouting. The packaging duopoly forming in AI silicon is not zero-sum: TSMC and Intel are splitting a market that is growing fast enough to accommodate both, with different package architectures optimized for different workload profiles.

TSMC's Response: Quasi-EMIB and Panel-Level Manufacturing

The competitive pressure from EMIB has not gone unanswered. TSMC is reportedly developing its own embedded-bridge architecture in partnership with Kinsus Interconnect Technology Corp., a Taiwan-based substrate manufacturer. The program is referred to internally as "quasi-EMIB" and would embed silicon bridges directly into the organic package substrate — closer to Intel's architecture than to CoWoS-L's redistribution-layer approach. When the program became public on July 30, TSMC shares rose 7.6 percent and Intel shares climbed roughly 13 percent — a dual stock rally on July 30 that market analysts read as evidence that the packaging market is large enough to reward TSMC for expanding its architectural toolkit while simultaneously validating Intel's approach. The TSMC quasi-EMIB program with Kinsus is being developed to prevent further customer migration from CoWoS to Intel's platform.

Separately, TSMC has been advancing CoPoS — Chip-on-Panel-on-Substrate — which shifts from round 300mm wafers to rectangular 310mm by 310mm (12.2 by 12.2-inch) panels for packaging. This directly addresses the geometric waste problem that gives EMIB its cost advantage at large package scales. Morgan Stanley's Asia-Pacific Technology team projected in mid-2026 that CoPoS could reach mass production as early as 2028, partly driven by competitive pressure from EMIB-T. Intel is already where TSMC is trying to get to on the geometry question — but TSMC's timeline for arriving is now substantially accelerated.

What Comes After Organic Panels: Glass

Beyond the current generation of organic panel-based packaging, both TSMC and Intel are pointing toward the same longer-term answer: glass core substrates. Glass offers several material advantages over organic alternatives: glass's coefficient of thermal expansion is approximately 3 parts per million per degree Celsius, far closer to silicon's 2.8 parts per million than organic substrates' 14 to 17 parts per million. That closer thermal match dramatically reduces the warpage that plagues large-format organic packages during thermal cycling — the same warpage problem that reportedly complicated Nvidia's Rubin Ultra four-die package design. Glass also enables through-glass vias at finer pitch than organic alternatives, permits optical interconnects to be integrated directly into the substrate, and supports processing at higher temperatures for more flexible power delivery and signal routing.

Intel demonstrated a 78mm by 77mm glass substrate package incorporating EMIB at NEPCON Japan 2026, and has said it solved the "SeWaRe" microcracking problem that arises when drilling through glass. Mass production of glass-core packages is targeted for later in this decade by both Intel and TSMC. Whoever industrializes glass substrate manufacturing at commercial yield first will hold the next phase of the packaging leadership position — and the race to that point is now accelerating on both sides of the Pacific.

What Hyperscalers and Chip Designers Should Understand

The packaging choice a hyperscaler or chip designer makes in the next 12 to 18 months will govern what their AI silicon can do — and how much it costs — through the end of this decade.

For training workloads requiring the highest-bandwidth CoWoS interposer performance, TSMC remains the clear path. The ecosystem depth, the process-node integration, and the proven production record at Nvidia-scale volumes are not quickly replicated. For inference ASICs and custom chips where package size, cost at volume, and supply-chain diversification are the governing constraints, Intel's EMIB-T is now a commercially validated alternative with real hyperscaler customers, a yield record above 98 percent, and a geometric advantage over CoWoS that compounds as AI packages grow. The decision is no longer theoretical, and the order books confirm it.

What ZDNet Korea's analysis this morning captures, and what the market's July 30 dual-stock rally already priced in, is that the AI chip packaging industry is completing its transition from a monopoly to a duopoly — structured not by which foundry is larger or more advanced, but by which workload each architecture is built to serve.

Frequently Asked Questions

What is the fundamental difference between CoWoS and EMIB in an AI chip package?

CoWoS uses a silicon interposer — a full layer of silicon spanning the entire package floor — to route connections between the AI processor die and high-bandwidth memory stacks. The interposer is built with thousands of tiny copper-filled vertical channels (through-silicon vias) that carry data at terabyte-per-second rates. Intel's EMIB instead embeds small silicon bridges directly in the organic package substrate, only at the exact spots where adjacent chips need to exchange high-speed data. Everything else is ordinary organic material. CoWoS delivers higher interconnect density across the whole package — important for training workloads where dense data movement happens everywhere simultaneously. EMIB delivers comparable bandwidth at the die interfaces that matter, eliminates the expensive silicon interposer (40 to 60 percent of CoWoS package cost), and can scale to larger package sizes without hitting the circular wafer geometry ceiling that limits CoWoS.

Why is Google switching its TPU packaging from TSMC CoWoS to Intel EMIB?

Google's Tensor Processing Units are inference-class custom chips — designed to run deployed AI models handling millions of simultaneous requests, not to train those models from scratch. Inference workloads need large packages that integrate many memory stacks alongside compute chiplets, but they do not require the extreme interconnect density across every millimeter of package floor that CoWoS provides. At the package sizes Google's next-generation TPUs require, EMIB-T's rectangular-panel geometry delivers approximately 90 percent substrate utilization versus approximately 60 percent for round-wafer CoWoS interposers, translating to roughly 50 percent lower packaging costs. With EMIB-T yield reaching approximately 98 percent in July 2026 — meeting mass-production standards — Google's commitment of three million TPUs for 2028 has become commercially executable. Supply-chain diversification away from a single packaging vendor also reduces geopolitical concentration risk.

If EMIB is cheaper and scales larger, why does Nvidia still use CoWoS for its training GPUs?

Nvidia's Blackwell and Rubin training accelerators run workloads where the matrix multiply operations require terabyte-per-second data movement in many directions across the entire package simultaneously. CoWoS's full silicon interposer provides lower interconnect latency and higher routing density across the complete package floor than EMIB's localized bridge approach can match at that level. The bandwidth gap at the highest-intensity training workloads means CoWoS's cost premium is justified for Nvidia's flagship products. EMIB is structurally better suited to inference and ASIC workloads that need larger packages and more memory stacks but do not require the all-directions, maximum-density interconnect that CoWoS delivers. Both architectures win the work they were built to do — which is precisely why the dual stock rally on July 30 rewarded both TSMC and Intel simultaneously.

What happens when both CoWoS and EMIB hit their scaling limits?

Both technologies face hard limits at extreme package sizes — approximately 14 times the photolithography reticle limit for CoWoS by 2029, with similar scale targets for EMIB. The common successor being developed by both Intel and TSMC is glass core substrates. Glass offers a coefficient of thermal expansion closer to silicon's, dramatically reducing the warpage that afflicts large organic-panel packages during heat cycling. It enables through-glass vias at finer pitch, allows optical interconnects to be embedded directly, and comes in rectangular panels that preserve EMIB-style geometric efficiency. Intel demonstrated a glass substrate package with EMIB at NEPCON Japan 2026, and TSMC is advancing its CoPoS panel-level program toward a glass roadmap. Whoever industrializes glass substrate packaging at commercial yield first will likely define the AI chip packaging landscape through the end of the decade.