On July 3, He Tingbo, the leader of Huawei Semiconductor, introduced the V2 iteration of the 'Time Scaling Theory for Multi-Level Electronic Systems'—a document widely recognized in the industry as 'Tao's Law'. In contrast to its predecessor, the V1 version, this updated edition is bolstered by comprehensive engineering implementation specifics, empirical quantitative data, and a detailed roadmap for product evolution. It strengthens the scaling theory framework for the post-Moore era, which is anchored around the time constant τ.

The V2 version is systematically structured into eight chapters, each with a more lucid logical flow. It incorporates numerous schematic and physical diagrams to elucidate core technologies, including the τ hierarchical spatiotemporal model. From an engineering standpoint, it offers a profound exploration of the gear ratio concept within LogicFolding, facilitating globally optimal vertical logic partitioning and surmounting the constraints inherent in conventional 3D stacking techniques.

Furthermore, the paper features a new table presenting empirical mass production data, providing pertinent parameters for the Kirin 2026 and the benchmark Kirin 9030 Pro. The full-scenario roadmap has also been refined, delineating key milestones in technological evolution. It expands on pathways such as the downward migration of mobile Through-Silicon Vias (TSVs) and multi-active layer stacking, while also specifying the iteration cadence for the AI Ascend series accelerators.