Intel said on June 16 that 18A-P, an enhanced version of its 1.8nm-class 18A process, has entered risk production — on the timeline it gave customers and partners last year. The company detailed the milestone at the 2026 VLSI Symposium, a leading semiconductor research conference.

For most foundries, an on-schedule node enhancement would be routine. For Intel it is the headline. The company's "five nodes in four years" roadmap was widely doubted, 18A itself drew reports of delays and yield struggles, and Intel's entire pitch to win foundry customers away from a dominant TSMC and a resurgent Samsung rests on proving it can execute predictably. Hitting a date it set with customers a year earlier is, in that context, the message Intel most wants to send — arguably more than any single performance number.

What "Risk Production" Actually Means

Risk production is the stage at which a process is frozen and run on production tooling so that early customers can commit their designs — at their own risk — before high-volume manufacturing yields are fully proven. It is a marker of readiness, not of volume. So the milestone says Intel is where it said it would be on the calendar; it does not yet say how many chips, at what yield, or for which external customers. Those questions come later in the ramp.

The Numbers, All Intel's Own

18A-P, which Intel calls the first performance enhancement in the 18A family, improves on 18A across performance, power, and area. By Intel's figures, presented at its VLSI talks, it delivers 9% higher performance at the same power, or 18% lower power at the same performance, with thermal resistance improved 20–40% through materials and design changes and via resistance reduced 10–30%. Crucially for customers, it uses the same design IP and design flow as 18A, so existing designs can carry over rather than being rebuilt — a practical detail that lowers the cost and risk of adopting the newer process. The node introduces Power Boost, a new dual-contact, low-resistance transistor option that Intel says raises drive current, and thus achievable operating frequency, while keeping transistor capacitance unchanged. These are vendor-reported lab and silicon measurements, not independently benchmarked results.

Why Putting the Power on the Back Matters

Intel also quantified gains from the gate-all-around (GAA) transistors and backside power delivery (BSPD) it unveiled last year — and BSPD is the change worth understanding, because it is one of the biggest levers for power-efficient AI silicon. In a conventional chip, the wiring that carries power and the wiring that carries signals compete for the same crowded space above the transistors. BSPD moves the power-delivery network to the back of the wafer, separating the two. That steadier power feed is why Intel reports a tenfold cut in dynamic voltage droop, freeing front-side tracks accounts for an 11% reduction in routed area, and the cleaner delivery lets the chip run faster at low voltage.

In a VLSI talk, Intel Foundry VP and Fellow Eric Karl reported those figures yield up to 6% higher frequency or more than 15% lower dynamic power versus a comparable front-side interconnect approach, with the advantage growing at low voltage: silicon measurements on CPU cores showed frequency rising more than 30% at around 0.5 volts. The lower the operating voltage, the more the separated power network pays off — exactly the regime data-center and AI chips increasingly run in.

A Look Further Down the Road

The company also previewed longer-range research, all still at the demonstration stage rather than in any product. It showed a complementary field-effect transistor (CFET) — widely seen as the successor to GAA — as a monolithic CFET inverter at a 45nm gate pitch, vertically stacking the NMOS and PMOS transistors that today sit side by side. In principle, stacking them halves the area a transistor pair occupies, enabling higher density than GAA. Intel further showed a subtractive ruthenium (sRu) interconnect with air gaps, saying ruthenium cuts parasitic capacitance about 35% versus copper to improve frequency, while air gaps between lines reduce interference and RC delay. Separately, it demonstrated monolithic integration of gallium-nitride power devices with silicon logic on 300mm wafers, aimed at more efficient power management.

The disclosures, led by Intel Foundry chief Naga Chandrasekaran, signal Intel's push to stay at the leading edge as 18A itself ramps toward production — a centerpiece of the company's bid to re-establish its foundry business against TSMC and Samsung. The harder test still lies ahead: turning an on-time node milestone into proven volume yields and, above all, into committed external customers, most of which are so far evaluating rather than building.

Frequently Asked Questions

What is risk production in semiconductors?

Risk production is a stage between development and high-volume manufacturing in which the process design is locked and run on production equipment, letting early customers commit their chip designs before yields are fully proven — hence "at their own risk." It signals that a node is ready for customers to build on, but it does not by itself indicate production volume, final yields, or commercial shipments.

What is Intel 18A-P?

18A-P is an enhanced version of Intel's 18A (1.8nm-class) manufacturing process and, Intel says, the first performance upgrade in the 18A family. The company reports it delivers 9% higher performance at the same power, or 18% lower power at the same performance, versus 18A, while remaining compatible with 18A's design rules so customers can reuse existing designs.

What is backside power delivery?

Backside power delivery (BSPD) routes a chip's power-supply wiring on the back of the wafer instead of crowding it alongside the signal wiring on the front. Separating the two gives transistors a steadier power feed, frees up front-side space for signal routing, and helps the chip run faster at low voltage. Intel markets its version as PowerVia and reports large reductions in voltage droop and routed area from it.

What is a CFET?

A complementary field-effect transistor (CFET) is a next-generation transistor structure, widely viewed as the successor to today's gate-all-around designs, that stacks the two transistor types (NMOS and PMOS) vertically instead of placing them side by side. In principle this roughly halves the area a transistor pair occupies, enabling greater density. Intel demonstrated a CFET inverter as a research milestone, not yet a product.