On June 17, 2026, SuanMiao Technology made a significant announcement: its 3D TokenPU chip, the A4E, tailored specifically for large-scale model inference, had officially completed its tape-out on June 15. This cutting-edge chip employs a 3D hybrid stacking architecture, stacking eight layers of memory wafers atop the computational logic wafer. Utilizing through-silicon vias (TSVs) and bump technology, it achieves micron-level interconnections, delivering an impressive memory access bandwidth of up to 16TB/s.

The A4E chip introduces a groundbreaking Tile-Native hardware-software collaborative approach. It features native hardware support for Tile-level data scheduling and multi-precision dynamic switching. On the software side, it boasts a compiler toolchain that seamlessly integrates with open-source ecosystems such as LLVM and Triton. Built on a self-developed RISC-V architecture, proprietary IP, and a self-developed software stack, the chip leverages a domestic supply chain and mature manufacturing processes, ensuring both innovation and reliability.

The core team at SuanMiao brings a wealth of experience, having successfully mass-produced over 10,000 3D hybrid stacking wafers. With research and development personnel making up over 80% of the workforce, the company is at the forefront of technological advancement. Currently, SuanMiao Technology has been engaged in nearly a year of in-depth R&D collaboration with leading providers of large-scale models. This collaboration ensures that the chip's design meets real-world inference scenario requirements from the very outset.

The company has successfully completed multiple rounds of financing, attracting investment from prominent entities such as China Development Bank Financial, Beijing Shunxi, Source Code Capital, Shixi Capital, Legend Star, and Xianghe Capital. This strong financial backing underscores the industry's confidence in SuanMiao's vision and technological prowess.