On October 15, during the 2026 Bay Area Chip Expo, Huang Yu, the Chief Scientist of Semiconductor EDA at Huawei, expounded on Huawei's Tao's Law. This law is structured across four distinct layers: The device layer focuses on optimizing transistor structures and interconnection techniques to minimize the time constant of devices at their origin. The link layer stands out as the pinnacle of innovation within this framework. The chip layer emphasizes collaborative software-hardware design, paving the way for a novel architectural approach. Lastly, the system layer encompasses super nodes and cabinet interconnections, necessitating enhanced communication protocols and accelerated data transfer rates.

Huang Yu emphasized that, apart from the challenges in process refinement, engineering, and system design, the most formidable obstacle confronting Tao's Law is the development and utilization of EDA tools.