Recently, Pan Quan’s research team from the Shenzhen-Hong Kong Microelectronics Institute (SHMIC) at the Southern University of Science and Technology (SUSTech) has made a notable breakthrough in the realm of high-speed wired chip design. Their findings were published in the IEEE Journal of Solid-State Circuits (JSSC), a premier journal in integrated circuit design, under the title [Insert Title Here]. The study introduces a single-ended orthogonal PAM-4 transceiver that leverages encoder-based crosstalk cancellation and linearity calibration techniques. Fabricated using a 28-nanometer CMOS process, the transceiver achieves an impressive data transmission rate of 2×56 Gb/s.

Through its innovative encoder-based crosstalk cancellation technology, the research effectively mitigates crosstalk challenges in high-density channels. Additionally, the incorporation of linearity calibration technology enhances signal quality. Test results demonstrate that the transceiver significantly improves both horizontal and vertical eye opening when operating under 56 Gb/s NRZ signals. Moreover, its energy efficiency reaches leading levels within the industry, providing a robust foundation for the practical deployment of high-density single-ended interconnect systems.