14-micron chips stacked in ten layers with almost zero offset: POSTECH quadruples chip stacking density compared to existing HBM
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Author:小编   

On July 8, 2026, a team led by Professor Seok Kim from the Department of Mechanical Engineering at Pohang University of Science and Technology (POSTECH), in collaboration with the Korea Institute of Industrial Technology, announced the successful development of a stable stacking technology for ultra-thin semiconductor chips. By integrating transfer printing with real-time bonding processes, this technology enables the stable stacking of over ten layers of 14-micron-thick silicon-based chips under mild conditions of less than 180°C and 20 kPa, achieving an integration density four times that of existing high-bandwidth memory (HBM). This technology addresses the industry-wide challenge of bending and fracture in ultra-thin chips, with minimal interlayer alignment errors and effectively suppressed chip warping. It significantly enhances AI semiconductor performance and is applicable to advanced chiplet integration and micro-LED display devices. The relevant findings have been published in the online edition of the international engineering academic journal Results in Engineering.