In 2026, Intel and AMD are set to jointly roll out the ACE CPU extension specification, which seamlessly integrates AI computing instruction sets into the x86 architecture. This innovative specification markedly boosts energy efficiency and computational density through the optimization of matrix multiplication, thereby lowering the threshold for running AI models locally on CPUs. ACE builds upon the existing AVX10 register architecture, introducing specialized hardware units tailored for matrix computation. This approach circumvents the need for extensive underlying architectural restructuring, thereby minimizing adaptation costs.

Official data reveals that, under identical input vector scales, ACE delivers a computational density 16 times greater than that of AVX10. It achieves this by reducing instruction scheduling overhead, enhancing memory bandwidth utilization, and optimizing power consumption control. The ACE instruction set boasts cross-vendor compatibility, enabling developers to craft a single codebase that seamlessly adapts to all ACE-supported CPUs from both Intel and AMD. This eliminates the cumbersome process of multiple adaptations, streamlining development efforts.

Mainstream AI frameworks, including PyTorch and TensorFlow, are fully compatible with ACE, supporting widely used AI data formats such as INT8, FP8, and BF16. Additionally, ACE provides native support for the OCP MX block scaling format, further enhancing its versatility. Looking ahead, new-generation x86 processors will incorporate ACE extensions, enabling laptops, desktops, servers, and other devices to effortlessly handle a variety of local AI tasks without the need for discrete graphics cards. This advancement broadens the application scenarios for edge AI, paving the way for a more intelligent and connected future.