TSMC unveiled its advanced process technology roadmap up to 2029 at the North American Technology Symposium this Wednesday, covering next-generation processes at the 1.2-nanometer and 1.3-nanometer levels (A12, A13), and unexpectedly revealed a new member of the N2 family, N2U. TSMC made it clear that, at least until 2029, all planned nodes will not require the introduction of High Numerical Aperture Extreme Ultraviolet Lithography (High-NA EUV) machines, and will continue to leverage existing equipment for technology scaling. According to the roadmap, A13 is an optically scaled-down version of A14, achieving approximately a 3% reduction in linear dimensions, about a 6% reduction in area, and around a 6% increase in transistor density through Design-Technology Co-Optimization (DTCO), while maintaining fully compatible design rules and electrical characteristics with A14. It is scheduled for production in 2029. N2U, as the third-generation extended version of the N2 platform, optimizes performance through DTCO technology, delivering approximately a 3%-4% performance improvement at the same power consumption, or an 8%-10% reduction in power consumption at the same speed, with a 2%-3% increase in logic density. It is compatible with N2P IP, supporting low-cost upgrades for clients' existing designs, and is expected to enter production in 2028. The A16 process, targeting artificial intelligence and high-performance computing (HPC), has postponed its mass production to 2027, adopting Super Power Rail (SPR) backside power delivery technology and integrating first-generation nanosheet GAA transistors, significantly outperforming N2 and N2P in terms of performance, power consumption, and transistor density. A12, as the next-generation node following A16, is expected to be introduced in 2029, adopting second-generation nanosheet GAA transistors and NanoFlex Pro technology, continuing to use backside power delivery, and achieving overall density improvements through frontside and backside scaling. Kevin Zhang, Senior Vice President of Business Development and Global Sales at TSMC, stated that the company adopts a differentiated strategy, segmenting leading-edge process nodes according to end-market demands, introducing a new node for client-side applications annually, and a new node for AI/HPC applications every two years, to balance performance, power consumption, and cost.