On April 22, 2026 (local time in the US), Rambus declared the rollout of a chipset solution tailored for LPDDR SOCAMM2 modules. This solution is specifically crafted to deliver low-power yet high-performance memory support for AI servers. It encompasses an SPD chip along with 12V and 3V voltage regulators. The SPD chip takes charge of module identification, configuration, and telemetry functions. Meanwhile, the voltage regulators facilitate localized and efficient power conversion, ensuring they meet the stringent power and signal integrity demands essential for high-speed LPDDR operation. As a next-gen enterprise-class memory standard, SOCAMM2 makes notable strides in performance, power efficiency, size, and maintainability. This is achieved through a modular design seamlessly integrated with LPDDR technology. It is anticipated to bridge the market gap between HBM and conventional DDR5.