According to information from the OpenBenchmarking database, engineering samples of AMD's next-generation EPYC Venice (Zen 6 architecture) have appeared on test platforms, covering multiple configurations ranging from 64 cores to 192 cores. This leak involves three SP7 evaluation boards named after African countries: Congo, Kenya, and Nigeria. The Congo platform tested two samples: one with 192 cores and 384 threads, a base frequency of 4.02GHz, paired with eight 64GB DDR5-8000 memory modules; the other with 64 cores and 128 threads, paired with four 64GB DDR5-6400 memory modules. The Kenya platform tested a sample with 128 cores and 256 threads, also running at 4.02GHz, paired with two 128GB DDR5-8000 memory modules. The Nigeria 2P dual-socket platform simultaneously tested three Zen 6 engineering samples with 64, 128, and 192 cores, configured with up to 32 64GB DDR5-8000 memory modules, totaling 2TB, and further expandable via higher-density modules. In terms of configurations, the 192-core version adopts an 8CCD+2IOD chip layout, with the dual-socket version featuring 2×(8CCD+2IOD); the 128-core version uses 4CCD+2IOD; and the 64-core version employs 2CCD+2IOD. Currently, all revealed samples are early engineering prototypes, leaving significant room for optimization in final performance. However, their performance already matches or approaches that of the official versions of fifth-generation Turin SKUs with the same core counts. AMD has previously stated that the Venice series will deliver a 70% performance improvement and a 30% increase in overall density, with an official release expected in the second half of this year. It will form the Helios AI computing platform alongside the new generation of Instinct AI accelerators.