With the global demand for AI and high - performance computing chips experiencing a dramatic upswing, advanced packaging technology has emerged as a pivotal factor. TSMC's CoWoS capacity has now become a central focus in the market. At present, this capacity is predominantly contracted by industry giants like NVIDIA, AMD, and major cloud service providers, including Google, Amazon, and Meta.

NVIDIA, in particular, is projected to dominate 63% of TSMC's CoWoS capacity in 2025. By 2026, it's expected to secure a staggering 60% of the global CoWoS demand, amounting to roughly 595,000 wafers. This demand is mainly driven by its AI accelerator chips, such as those built on the Rubin architecture. AMD and Broadcom are set to account for 11% and 15% of the capacity respectively, while other customers like Amazon and Marvell will collectively make up around 14%.

To meet this growing demand, TSMC is ramping up its capacity. It's expanding its packaging facilities in the Tainan and Chiayi Science Parks, with a total investment surpassing RMB 44.6 billion. By 2025, the monthly capacity is anticipated to reach between 65,000 and 75,000 wafers, doubling from the 2024 levels. Moreover, it's expected to further increase to 93,000 wafers by the end of 2026.

However, despite these expansion efforts, the ongoing explosive growth in AI chip demand poses a challenge. The global CoWoS demand is projected to hit 1 million wafers by 2026, leaving new customers grappling with tight capacity scheduling issues. To address this, TSMC is partnering with packaging and testing firms like ASE and Amkor to boost production and ease the supply - demand imbalance.