Optical connectivity is moving progressively closer to the compute core, with chip-to-chip links and new memory architectures emerging as the next frontier after optical scale-up networks, according to Dr. Julie Sheridan Eng, EVP, Optical Components and Chief Technology Officer at Coherent. Speaking at PECC Summit on October 20, Eng outlined a future in which pluggable transceivers, co-packaged optics (CPO) and near-packaged optics (NPO) coexist, with different technologies addressing distinct requirements for reach, power, bandwidth density and serviceability.

Eng traced that progression from long-haul telecommunications through enterprise and hyperscale data centers to today’s AI infrastructure. Enterprise networks adopted multimode fiber and gallium arsenide VCSELs, while hyperscale facilities expanded demand for single-mode fiber, indium phosphide devices and silicon photonics. Multiple optical lanes, PAM4 modulation and digital signal processing subsequently increased transceiver capacity. AI now places greater pressure on bandwidth density and energy efficiency as optics becomes part of the fabric connecting distributed computing resources.

For scale-out networks, Eng described a continuing roadmap for pluggable optics built around higher lane speeds and denser packaging. Coherent has demonstrated 400G-per-lane links using differential electro-absorption modulated lasers and silicon-photonics modulators. At the recent ECOC exhibition in Málaga, the company demonstrated a 3.2T architecture in an OSFP-size package using eight 425G PAM4 optical lanes. These are technology demonstrations supporting the next generation of pluggables, rather than announcements of general product availability.

For scale-up connectivity, Eng emphasized the trade-offs between CPO and NPO. Placing optical engines beside a switch ASIC or accelerator shortens electrical connections, supporting signal integrity and potentially lower power. NPO places the optical engine on the circuit board near the processor, offering greater serviceability and flexibility while requiring signals to traverse additional board traces and connectors. Eng expects NPO deployments in 2027 and identified Coherent’s participation in the Open CPX MSA as part of the effort to develop a socketed ecosystem.

The longer-term opportunity is moving optical links inside advanced packages as bandwidth requirements between compute and memory increase. Eng’s presentation illustrated an optical interposer connecting XPUs and high-bandwidth memory, with external laser sources, wavelength-division multiplexing and circulators. Candidate implementations include silicon photonics powered by external ultra-high-power or integrated high-power InP lasers, alongside high-density VCSEL arrays connected through fiber arrays or multicore fiber. Eng placed these emerging chip-to-chip and memory-disaggregation applications toward the end of the decade.

Manufacturing remains central to that transition. During the discussion, Eng identified electrical crosstalk and matching driver pitch to dense optical arrays as practical challenges, alongside optical crosstalk and fiber integration. She also stressed that wafer-level integration must deliver reproducible performance and sufficiently high yields to achieve its cost advantages. On supply, Eng said Coherent’s InP capacity was essentially sold out through the end of 2027, with expansion underway to address demand.

• Pluggables: Higher lane speeds and denser packaging extend the scale-out roadmap.

• CPO: Short electrical paths support bandwidth density and power efficiency.

• NPO: Socketed optical engines offer serviceability and implementation flexibility; Eng expects deployments in 2027.

• Chip-to-chip: Optical compute-and-memory connections represent a longer-term opportunity toward decade-end.

• Technology choice: Silicon photonics, InP and VCSEL architectures address different reach, density, power and cost requirements.

Analysis

Eng’s presentation points to several optical transitions occurring simultaneously. Higher-speed pluggables continue to address scale-out fabrics while CPO and NPO bring optical conversion closer to switching and accelerator silicon. Coherent’s published demonstrations reflect that breadth: its OFC portfolio included a 6.4T silicon-photonics CPO implementation, a VCSEL-based multimode approach and a 400G-per-lane InP modulator. The company’s PhotonLink platform brings together technologies and assembly capabilities for these different implementations.

Chip-to-chip optics introduces a deeper architectural change because it extends optical connectivity into the relationship between processors and memory. The slide’s emphasis on multiple wavelengths, multiplexers and circulators also shows that increasing bandwidth alone is insufficient: designers must manage fiber count, routing complexity and packaging density. Eng’s discussion identifies the practical milestones to watch—driver integration, crosstalk control, optical coupling and manufacturing yield—before these architectures can progress from demonstrations to repeatable production.