Japan has placed a concrete manufacturing bet on silicon spin qubits: Hitachi, Ltd. announced on July 22 that it has been selected by Japan's New Energy and Industrial Technology Development Organization (NEDO) to lead a government-funded initiative that will fabricate quantum processors using Intel's 18A semiconductor process — currently one of the most advanced chip-manufacturing nodes in high-volume production anywhere in the world. The project pairs Hitachi with Intel's Japanese subsidiary, Intel K.K., and the National Institute of Advanced Industrial Science and Technology (AIST), and it expands a broader strategic collaboration the two companies announced on June 5, 2026.

The core claim the project stakes is structural: that the fastest path to scalable quantum computing runs through existing semiconductor fabs, not through bespoke laboratory hardware. Rather than building a single demonstration machine, the consortium will construct the engineering stack — chip designs, manufacturing toolkits, cryogenic packaging, cloud infrastructure — needed to produce silicon quantum processors at industrial scale. The deliverable that will matter most for the broader quantum computing industry is not the qubit count milestones but the silicon quantum process design kit the project will develop and make available for external use. A production-grade quantum PDK is the interface that would allow any chip design team in the world to build silicon spin-qubit hardware on an industrial fab without rebuilding from scratch the manufacturing knowledge that Hitachi and Intel will encode in that toolkit.

Silicon spin qubits encode quantum information in the spin state of a single electron trapped in a quantum dot — a nanoscale region roughly 50 nanometers across, defined by voltage-controlled gate electrodes patterned in silicon. The electron can be spin-up or spin-down, or a quantum superposition of both. Logic operations are performed by applying microwave pulses at the electron's resonance frequency; two-qubit gates exploit the exchange interaction between electrons in adjacent quantum dots.

Why Silicon Spin Qubits, and Why Intel 18A

Quantum computers encode information in qubits — units that exploit quantum mechanical properties to represent not just 0 or 1 but superpositions of both simultaneously. The practical problem is that qubits are exquisitely fragile. Heat, vibration, stray electromagnetic fields, and imperfect control signals introduce errors continuously. Reaching fault-tolerant quantum computing — the regime where a machine corrects its own errors reliably — is expected to require roughly one million physical qubits under current engineering assumptions, according to estimates for running Shor's algorithm at full scale.

Several hardware approaches are competing to reach that scale. What makes silicon spin qubits strategically distinct is not their current qubit counts — which lag behind superconducting systems from IBM and Google — but their manufacturing compatibility. Unlike superconducting qubits, which require niobium-based deposition equipment and bespoke cryogenic packaging not found in commercial fabs, silicon quantum dots can be fabricated using the same extreme-ultraviolet lithography, ion implantation, and gate-stack deposition processes that run in mainstream CMOS production lines. The critical dimensions required are within the capabilities of advanced process nodes, including Intel 18A.

Intel 18A is a 1.8nm-class semiconductor node that entered high-volume manufacturing in late 2025. It introduced two architectural advances simultaneously. RibbonFET is Intel's implementation of gate-all-around transistor architecture, in which the gate electrode wraps around all four sides of a silicon nanosheet channel, delivering tighter electrostatic control than prior FinFET designs. PowerVia moves the power delivery network to the backside of the wafer, freeing the front-side routing layers for signal connections. Together, those two innovations deliver up to 18% higher performance at identical power consumption, or 38% lower power at identical performance, compared to Intel 3.

Both properties matter for quantum chips. RibbonFET's improved gate control reduces transistor-to-transistor variability — the same manufacturing precision that affects quantum dot uniformity and qubit yield. PowerVia's backside power delivery frees routing layers that would otherwise compete for space with the dense gate arrays needed to address individual qubits. The Intel 18A process design kit, which packages the manufacturing rules and simulation models for that node, is what allows Hitachi's engineers to design qubit chips that Intel's fabs can reproducibly manufacture — without renegotiating process parameters for every tape-out.

Four Technical Pillars the Project Will Build

The NEDO initiative, which runs through March 2029, is organized around four interlocking workstreams:

Industrial-scale 100-qubit chip designs. Hitachi and Intel K.K. will co-develop qubit chip architectures targeting at least 100 qubits while maintaining the manufacturing consistency expected from semiconductor production lines — meaning yield and performance must be controllable across wafers, not just demonstrated in a single laboratory device. The project will also engineer the peripheral control circuits and cryogenic packaging needed to address each qubit reliably at operating temperatures near absolute zero (roughly 10 to 20 millikelvin, or about −459°F / −273°C).

A silicon quantum process design kit. Building this PDK is the project's most industrially consequential deliverable. In classical chip design, PDKs are what allow hardware engineers to design chips against a fab's production rules without needing to understand its internal process chemistry. In quantum computing, no such standardized tool currently exists for silicon spin-qubit platforms on advanced process nodes. Once the Hitachi-Intel PDK is established, engineers at universities, startups, and corporate labs could design silicon quantum chips for Intel's fab using the same design workflow that classical chip designers use — dramatically lowering the barrier to hardware development worldwide.

3D integration for 1,000-qubit systems. The wiring bottleneck is the central engineering problem for silicon spin qubits at scale. Each qubit requires dedicated gate, control, and readout connections at millikelvin temperatures. As qubit counts rise, routing those connections from room-temperature electronics into a dilution refrigerator consumes the refrigerator's limited cooling budget — roughly 30 microwatts at the coldest stage — long before a meaningful qubit array can be assembled. Hitachi will develop high-density 3D packaging technologies — stacking qubit chips and control electronics vertically — designed to operate at cryogenic temperatures with short, dense interconnects that sidestep the long wire runs. This is specifically aimed at the 1,000-qubit generation.

Cloud access through AIST's G-QuAT. Hitachi and AIST will build a cloud platform giving external researchers remote access to experimental silicon quantum hardware through AIST's Global Research and Development Center for Business by Quantum-AI Technology (G-QuAT). The G-QuAT facility, developed at a cost of approximately ¥62 billion (approximately $380 million USD — exchange rate as of July 23, 2026; conversions are approximate), already hosts quantum computing systems and hybrid quantum-classical computing infrastructure.

What Silicon Spin Qubits Still Cannot Do

The 100-qubit and 1,000-qubit milestones the NEDO project targets represent research-scale achievements, not fault-tolerant computing. Running quantum error correction at the 100-qubit scale means a prototype implementing a quantum error-correcting code — not a machine performing reliable logical computation. Surface code error correction, the most widely studied approach, requires hundreds to more than a thousand physical qubits per single logical qubit. A machine that reaches a thousand physical qubits might support tens of logical qubits — enough to run research algorithms but far short of the roughly one million physical qubits expected for applications like breaking RSA-2048 encryption or running large-scale molecular simulation.

Silicon spin qubits also lag competitors in qubit count today. Fujitsu and RIKEN's parallel NEDO-backed program — using superconducting qubits rather than silicon — deployed a 256-qubit system in April 2025 and is targeting 1,000 qubits in fiscal 2026. IBM's superconducting roadmap and Quantinuum's trapped-ion systems are also operating on similar or more aggressive timescales.

The wiring bottleneck remains genuinely unsolved at scale. Maud Vinet, CEO of Quobly — a CEA-Leti and CNRS spinoff — said in 2025 that current prototypes rely on wiring that "isn't scalable" and that cryogenic CMOS integration is "essential for reducing wiring and minimizing latency — especially for quantum error correction." The 3D packaging work Hitachi is pursuing addresses exactly this constraint, but it has not yet been demonstrated at the qubit counts the project targets.

Gate fidelity on silicon spin qubits has been advancing rapidly. Hitachi published 99.1% single-qubit gate fidelity on natural silicon in October 2025, approaching the error thresholds at which quantum error correction codes can begin suppressing errors rather than amplifying them. But sustaining that fidelity across hundreds or thousands of qubits on a production wafer — where atomic-level variations in the silicon substrate can alter qubit properties from site to site — is a separate, unsolved yield problem.

Japan's Larger Strategic Position

The NEDO project fits within a sweeping national quantum strategy that Japan has been building since 2022. The Cabinet Office's Quantum Future Society Vision and Quantum Future Industry Strategy designated quantum computing, quantum communications, and quantum sensing as national priorities, with government funding through MEXT, NEDO, and JST exceeding ¥150 billion (approximately $920 million USD) committed across the national strategy period. Japan's Moonshot Research and Development Programme, Goal 6, targets a fault-tolerant universal quantum computer by 2050.

Hitachi's quantum pedigree runs deep. The company has been developing silicon quantum-dot qubits since the early 2000s and holds 15 patent families in the silicon spin-qubit space. It has participated in Japan's Moonshot Programme and collaborated with RIKEN and imec — the Belgian semiconductor research institute that demonstrated full-wafer EUV-patterned silicon spin qubits at IEDM 2025. Hitachi is also a member of the Quantum Strategic Industry Alliance for Revolution (Q-STAR), which includes Toyota, NEC, Fujitsu, NTT, and more than 100 other corporate members.

The project's timing coincides with accelerating global quantum manufacturing activity. GlobalFoundries launched a dedicated quantum foundry business unit in May 2026, and Quobly — the French silicon spin startup — announced that its silicon-spin processor would join OVHcloud's European sovereign cloud in late 2026. On the same day as the Hitachi-NEDO announcement, IBM announced plans to acquire HRL Laboratories, a silicon spin qubit research leader, suggesting the competitive landscape for silicon spin manufacturing is consolidating rapidly.

Why an Open Silicon Quantum PDK Changes the Equation

The NEDO project's roadmap includes a deliverable that the executive statements and press coverage have not foregrounded but that may ultimately prove the project's most significant contribution: the silicon quantum process design kit developed on Intel 18A, intended to be available to external researchers.

In classical semiconductor design, open PDKs — like the SkyWater 130nm PDK that enabled low-cost university chip fabrication, or the GlobalFoundries 180nm open PDK — transformed chip design from an activity requiring expensive fab relationships into one accessible to any team with standard electronic design automation software. Every major wave of semiconductor democratization has followed the establishment of a shared design interface. A silicon quantum PDK on Intel 18A would be the first such interface for advanced-node quantum chips: a common design language allowing any team to design silicon spin-qubit hardware for industrial fabrication without replicating the process development that Hitachi and Intel will encode in it.

This is the mechanism behind AIST G-QuAT Deputy Director Masahiro Horibe's statement that the initiative would "accelerate the formation and expansion of the ecosystem." Ecosystem formation in semiconductors does not happen through headcount additions at incumbents — it happens when external engineers can design and manufacture without asking permission from the technology's original developers.

Qubit Roadmap

The project outlines three milestones extending beyond the NEDO program's March 2029 conclusion:

Fiscal 2027 will see the launch of an initial cloud service providing external researchers access to silicon quantum hardware via G-QuAT, with services expanded in subsequent years. Fiscal 2028 is targeted for a 100-qubit silicon quantum computer prototype implementing quantum error-correcting codes — the first major milestone on the path toward fault tolerance. Fiscal 2030 is the target for a 1,000-qubit scale, 3D-integrated silicon quantum processing platform.

Hitachi CTO Shigetoshi Samejima described the project in terms that connect quantum computing to the company's existing enterprise strategy: the effort, he said, aims to "support future social infrastructure and industrial systems" while driving the company's Lumada digital services business forward. Intel K.K. President Makoto Ohno described the collaboration as establishing "foundational chip design, manufacturing and packaging technologies needed to move silicon quantum computing from research demonstration toward scalable industrial application."

Frequently Asked Questions

How do silicon spin qubits work, and why does CMOS compatibility matter?

A silicon spin qubit stores quantum information in the spin state of a single electron trapped inside a nanoscale region of silicon called a quantum dot. Gate electrodes patterned above the silicon control which electrons are confined and how they interact. The reason CMOS compatibility matters is that the lithography, materials, and equipment needed to build these structures already exist at scale in commercial chip fabs — the same tools that manufacture the processors inside smartphones and laptops. No other major qubit technology shares this manufacturing heritage, which means silicon spin qubits are the only qubit type that could, in principle, scale using existing industrial infrastructure rather than requiring entirely new production lines.

What is a process design kit, and why does a silicon quantum PDK matter?

A process design kit (PDK) is a collection of manufacturing rules, device models, and design constraints that semiconductor designers use to build chips compatible with a specific fab's production process. Without a PDK, designing a chip for a particular fab requires manual coordination with process engineers on every design decision. In classical chip design, shared PDKs made it possible for thousands of independent design teams worldwide to build chips without needing fab relationships or internal process expertise. A silicon quantum PDK on Intel 18A would do the same for quantum chip design: any engineering team with standard chip design tools could build silicon spin-qubit hardware for industrial fabrication, rather than requiring the kind of in-house process knowledge that currently limits silicon quantum development to a small number of well-resourced institutions.

How does this Japan-US collaboration compare with other quantum computing efforts globally?

The Hitachi-Intel-AIST project is one of several parallel efforts to bridge the gap between quantum research and industrial manufacturing. In the US, GlobalFoundries launched a quantum foundry unit in May 2026. In France, Quobly is fabricating silicon spin qubits on STMicroelectronics' commercial FD-SOI line and will offer cloud access through OVHcloud in late 2026. IBM announced plans to acquire HRL Laboratories — a leading silicon spin qubit research institution — on July 23, 2026. The distinguishing feature of the NEDO project is its explicit focus on an advanced-node (1.8nm-class) process with a shared PDK deliverable, which positions it as an attempt to set a manufacturing standard rather than build a proprietary capability.

When will silicon spin quantum computers be available to use?

Cloud-based access to experimental silicon quantum hardware via AIST's G-QuAT facility is targeted for fiscal 2027 — meaning by March 2028. That access will be for research and experimental workloads, not general-purpose computing. The 100-qubit prototype implementing quantum error-correcting codes is targeted for fiscal 2028. The 1,000-qubit platform is targeted for fiscal 2030. Fault-tolerant quantum computing — where machines reliably correct their own errors and can run commercially useful algorithms — is expected to require on the order of one million physical qubits. None of the NEDO project's milestones reach that threshold; they represent intermediate research achievements on the path toward it.