In the post-Moore era, the traditional approach of geometric scaling for transistors has shown signs of deceleration, posing a challenge to the cost-efficiency and large-scale deployment of high-performance AI chips. To overcome this hurdle, innovative paradigms, notably the 'Tao (τ) Law,' have been introduced. These paradigms emphasize the 3D stacking of multifunctional chips to minimize system-level latency and boost equivalent integration density. At the network's edge, information processing grapples with issues such as latency, power consumption, and the overhead associated with data access. Hence, embracing a three-dimensional integration architecture—where sensing, caching, and computing units are vertically stacked atop the core logic processing unit—has emerged as a pivotal technical pathway. This strategy facilitates the creation of edge AI chips that boast low latency, high energy efficiency, and the capability to 'integrate sensing, caching, and computing' seamlessly.