As the AI industry experiences an unprecedented surge in demand for computing power, storage performance bottlenecks have become a pressing issue. This has prompted DRAM and NAND flash memory manufacturers to explore technological innovations. High Bandwidth Memory (HBM), for instance, faces challenges such as constrained production capacities, limited capacity per stack, and inter-chip transmission delays. While NAND flash memory is known for its cost-effectiveness and high capacity, its relatively slow transmission speed remains a drawback. To address these issues, SanDisk has introduced its High Bandwidth Flash (HBF) technology, which adopts a hierarchical architecture akin to HBM, boasting a single-stack capacity of up to 4TB. SanDisk’s latest patent introduces a 3D stacking architecture that integrates NAND flash memory storage dies—equipped with CMOS Bonded Arrays (CBA)—beneath the primary compute die, while simultaneously incorporating HBM DRAM on the same interposer. This design effectively segregates tasks: HBM manages low-latency, high-priority operations, while NAND handles extensive data read/write tasks. The use of wide-channel interconnections minimizes latency, cost, and power consumption. However, the patent is currently at the theoretical stage, and transitioning to mass production will require overcoming challenges related to power consumption management and manufacturing costs. It remains to be seen whether SanDisk can successfully commercialize this advanced architecture.