A logo is pictured on a Huawei NetEngine 8000 Intelligent Metro Router during a 5G event in London, on February 20, 2020. ISABEL INFANTES/AFP via Getty Images

Huawei moved its most important AI chip accelerator forward by three quarters at its flagship HUAWEI CONNECT 2026 conference Wednesday — and simultaneously became the initiator of the international standards project that will define how next-generation AI superclusters transmit data. Together, the two announcements mark a structural shift: China's leading AI chip maker is no longer merely catching up to Western AI infrastructure; it is shaping the rules that the rest of the industry must now follow.

Wang Tao — also known by his English name David Wang — Huawei's rotating chairman, opened the three-day event at the Shanghai World Expo Exhibition and Convention Center with a keynote titled "Intelligent Future: Building the Silicon-Based Soil for the Intelligent World." He announced that the Ascend 960DT, the training-optimized variant of the next Ascend generation, is now scheduled for commercial availability in Q1 2027 — three full quarters ahead of the Q4 2027 target that Huawei itself published just 12 days ago in its official roadmap communications. A second model, the Ascend 960PR, optimized for prefill and recommendation inference workloads, will follow in Q3 2027 — one quarter early.

The performance claim Wang presented: each Ascend 960 chip will deliver roughly double the compute of its 950-series predecessor, continuing the cadence Huawei has named the τ (Tau) Scaling Law — a framework proposed earlier this year by He Tingbo, president of Huawei's HiSilicon semiconductor subsidiary, at the ISCAS keynote in Shanghai in May 2026. Under that trajectory, the Ascend 970 is planned for 2028 and the Ascend 980 for 2029, locking in what Wang described as "one generation per year."

Every performance figure Huawei announced Wednesday comes from Huawei's own engineering team. No independent benchmarking organization has validated the doubling claim for the Ascend 960 series. The prior generation — the Ascend 950DT — was described by DeepSeek founder Liang Wenfeng in a July 2026 investor call transcript as trailing Nvidia's current hardware by roughly a four-to-one GPU equivalence ratio and approximately two years in development. That gap is real and should be the baseline assumption until independent auditors measure the Ascend 960 in production.

Huawei Initiated the AI Interconnect Standards Project in May — Before Building the Hardware

The more consequential announcement Wednesday was not the chip roadmap. It was the Near-Package Optics (NPO) supernode architecture that Wang unveiled as the core of the Ascend 960 SuperPoD — and the fact that the international standard project governing NPO was already approved at Huawei's initiative two months before this product was announced.

In May 2026, the Optical Internetworking Forum (OIF) — the 170-member international consortium that has governed interoperability for optical networking products since 1998 — approved a new 12.8-terabit-per-second NPO module standards project at its Q2 2026 plenary meeting in Malta, formally launching the new 12.8 Tb/s NPO project. Huawei initiated and advocated the proposal, engaging cloud operators, equipment vendors, optical module suppliers, chip vendors, and research institutes across the United States, Canada, China, and Japan. More than 40 companies are now participating in the standard's development. On September 10 — one week before this article — the International Photonics and Electronics Committee (IPEC) co-hosted an NPO Standards Industry Summit with OIF at the Shenzhen World Exhibition and Convention Center, in which Broadcom, Alibaba Cloud, Tencent, Baidu, and CAICT (China's state-run information and communications technology research institute) all participated alongside Huawei, reaching NPO standards consensus.

The Ascend 960 SuperPoD is the first product built on that standards project. Huawei's Hi-ONE optical interconnect module — which it describes as the industry's first mass-produced NPO product with a built-in light source — implements the architecture the OIF has now formally initiated as a global standard. Every competing vendor that adopts the OIF 12.8 Tb/s NPO standard will be implementing, in some form, a design Huawei brought to the standards body first.

That sequence — win the standards vote, then ship the product — is how platform advantages get locked in. It is also how a company operating under US sanctions and without access to the world's leading-edge fabrication equipment positions itself as an infrastructure rule-setter rather than merely an alternative supplier.

What NPO Is and Why the Power Math Matters

Near-Package Optics is a class of optical interconnect architecture that sits between traditional pluggable modules and Co-Packaged Optics (CPO), the most integrated form that melds optics directly onto the chip substrate.

In a conventional AI data center, high-speed 800G pluggable optical modules insert into front-panel switch slots. The signal travels from those front-panel ports across PCB traces — sometimes 20 to 30 centimeters — to reach the accelerator ASIC. To compensate for signal degradation over that distance, digital signal processors (DSPs) and clock data recovery (CDR) circuits sit in the path, retiming and re-amplifying the signal. Those retimer chips consume significant power and add measurable latency.

NPO relocates the optical engine from the front panel to within roughly 5 centimeters of the accelerator chip itself, mounted directly on the PCB substrate near the ASIC area. Because the electrical path between the optical engine and the chip is now centimeters rather than tens of centimeters, the DSP retimer chips can be eliminated, cutting power consumption and latency together. The trade-off compared to CPO is serviceability: NPO optical engines remain detachable (they can be replaced without replacing the ASIC), while CPO integrations are permanent — an advantage for data centers where hardware failures must be serviced at component level.

The specific arithmetic of Huawei's Hi-ONE deployment for the Ascend 960 SuperPoD: replacing 48,000 conventional 800G optical modules with 5,500 Hi-ONE units cuts power by over 550 kW per SuperPoD, per Huawei's figures. A 550 kW reduction per SuperPoD is not a footnote — it is the difference between a 5 MW and a 4.45 MW data center power budget per cluster, which at current US commercial electricity prices of roughly $0.10 per kilowatt-hour represents real operational savings at scale. The Hi-ONE module achieves 7.2 terabits per second of single-engine transmission capacity, with a built-in light source that Huawei claims is an industry first for a mass-produced NPO product.

CPO — the technology that would supersede NPO by integrating optics directly onto the chip package — is not expected to enter production at scale until at least 2028, according to industry forecasts. The TrendForce-projected CPO/NPO market size is expected to grow from approximately $100 million in 2025 to over $39 billion by 2030. Huawei has positioned its Hi-ONE product at the entry point of that growth curve — with an international standards project behind it.

System Scale: From 4,096 Cards to One Million Processors

The Ascend 960 SuperPoD unveiled Wednesday connects 4,096 Ascend 960 accelerator cards into a single unified computing node, delivering what Huawei claims is up to 8 exaflops of FP8 compute and 1 petabyte of HBM memory capacity, per Huawei's Connect 2026 announcement. These figures are Huawei self-reported and carry the same caveat as all prior Ascend performance claims: no independent third-party benchmarking organization has verified them.

The architectural logic, however, is not dependent on the specific numbers being accurate. The Ascend family's competitive strategy has always been to offset individual chip performance gaps against Nvidia by linking vastly more chips into a single logical machine via a memory fabric interconnect, rather than competing chip-for-chip on arithmetic throughput. The Ascend 950 generation demonstrated that strategy works at 8,192 chips: DeepSeek confirmed its V4 model runs on Ascend 950 clusters at production scale for inference workloads after months of co-engineering work with Huawei to adapt the model to the CANN software stack.

The Ascend 960 era extends that strategy to a new order of magnitude. Wang announced that Huawei's Lingqu UnifiedBus — the fourth generation of the company's proprietary memory-fabric interconnect — can now support clusters of up to one million processors in a single logical compute fabric. For comparison, Nvidia's NVLink 4 interconnect links up to 576 GPUs in the GB200 NVL576 configuration. A one-million-processor interconnect, if realized, represents a qualitatively different class of AI compute infrastructure from anything currently deployed at scale anywhere in the world.

Wang also reported that more than 1,000 Ascend 910C SuperPoDs have already been deployed in commercial data centers, and that the Ascend 950 SuperPoD is in volume commercial use — evidence that the underlying architecture is no longer a preview but an operational reality in China's AI infrastructure.

What Huawei Did Not Announce: Eleven Chips, One Ecosystem

Alongside the Ascend 960 processors, Huawei introduced more than ten additional AI-related chipsets at CONNECT 2026, covering inference, training, storage, interconnect, and system management functions — all integrated under the UnifiedBus architecture, according to reporting by Nikkei Asia covering the conference. This full-stack approach mirrors Nvidia's platform strategy, in which the GB200 NVL processors are embedded within a broader NVLink/NVSwitch/InfiniBand ecosystem that makes individual chip performance only part of the competitive equation.

Why Nvidia's Market Concession Is Already Priced In

The US export controls that progressively restricted Nvidia's ability to sell advanced chips in China — beginning in 2022 and tightening in 2023, 2024, and through subsequent revisions — created the conditions for Wednesday's announcement by removing Nvidia from the leading-edge Chinese market while demand for AI compute there accelerated.

Analyst estimates from Bernstein Research cited by multiple trade publications project Nvidia's 2026 China AI chip market share at approximately 8%, down from roughly 40% the prior year. Nvidia's chief executive Jensen Huang acknowledged the dynamic in plain terms in a May 2026 CNBC interview, saying Nvidia had conceded China's AI market to Huawei — calling it a "$50 billion opportunity this year alone" with nearly half the world's AI researchers based there. Nvidia CFO Colette Kress confirmed on a recent earnings call that H20 chip deliveries to China — the last Nvidia product legal to ship there under prior export control rules — have fallen to near zero.

Huawei's AI chip revenue is projected to reach approximately $12 billion in 2026, a roughly 60% increase from $7.5 billion in 2025, driven by surging orders for its Ascend 950 family. The most visible data point for that demand: DeepSeek, the Hangzhou AI lab whose January 2025 model releases rattled Western AI markets, placed an order for 160,000 Ascend 950DT accelerators for a gigawatt-scale data center in Inner Mongolia in what Bloomberg reported September 4 as one of the largest known deployments of domestically manufactured Chinese AI chips.

What Huawei Cannot Yet Do: The Manufacturing Ceiling

Wang's keynote did not address the binding constraint on every accelerated roadmap announcement Huawei has made: manufacturing capacity.

The Ascend 950 family is fabricated on SMIC's N+3 process node — broadly estimated as a 5-nanometer-class process built with deep ultraviolet (DUV) lithography rather than the extreme ultraviolet (EUV) equipment that TSMC uses for Nvidia's most advanced chips. SMIC's leading-edge facility is reportedly running above 93% utilization, according to Huawei supply chain analysis, and the plant produces roughly 60,000 wafer starts per month in 2026.

The more acute constraint is not wafers but high-bandwidth memory (HBM). AI accelerators require multiple stacks of high-speed HBM memory per chip. Export controls have cut off Huawei's prior access to Samsung and SK Hynix HBM. China's domestic alternative — ChangXin Memory Technologies (CXMT) — is projected to produce approximately 2 million HBM stacks in 2026, which is sufficient for roughly 250,000 to 300,000 Ascend 910C-equivalent chip packages, according to SemiAnalysis production estimates. That arithmetic creates a hard ceiling: SMIC can produce die for more chips than CXMT can supply with memory.

For the Ascend 960, which is expected to require equal or greater HBM content per chip than the 950 series, the production volume ceiling in 2027 will depend on whether CXMT achieves its HBM3e production capability and how quickly it scales output. Analysts track CXMT's Hefei, Shanghai, and Beijing facility expansions as the most strategically important domestic semiconductor development in China after Huawei's chip design itself.

The CANN software ecosystem — Huawei's counterpart to Nvidia's CUDA — adds a second structural constraint. CUDA has accumulated more than 15 years of ecosystem development and approximately 3 million active developers. CANN's developer community is estimated at roughly 87,000. DeepSeek required months of dedicated co-engineering effort to port its V4 model to Ascend hardware — and the porting process required rewriting more than 200 core CUDA operators for CANN's Next framework. That is not a barrier Huawei's hardware roadmap can resolve; it is a software ecosystem maturation problem that takes years.

China's National Intelligence Law: What Ascend Infrastructure Means for Data

For enterprises building AI infrastructure on Huawei's Ascend platform, the legal framework governing that infrastructure operates alongside the technical framework.

China's National Intelligence Law (2017): Article 7 of China's National Intelligence Law requires that "all organizations and citizens shall support, assist, and cooperate with national intelligence work in accordance with the law." This obligation applies to Huawei and to every company incorporated in China, regardless of where the hardware is physically located, what its stated privacy policy says, or whether a Chinese company has established a Western subsidiary. China's data and cybersecurity laws add localization and government-access provisions that operate alongside the intelligence law.

What this means for Ascend 960 infrastructure: Any AI workload — training runs, inference queries, model outputs, intermediate activations — processed on Ascend-powered infrastructure under Chinese enterprise control is subject to this legal framework. For Chinese enterprises using Huawei cloud services or on-premises Ascend clusters, this is the operating legal environment. For international enterprises considering Ascend infrastructure deployed in China or operated by Chinese entities, this is a fixed legal condition that no contractual privacy agreement can override.

The export control overlay: The US Bureau of Industry and Security ruled in May 2025 that Huawei's Ascend 910B, 910C, and 910D AI chips are prohibited for all persons — US and non-US — to use, sell, export, or finance. The Ascend 960 is not yet covered by an equivalent prohibition; no BIS ruling targeting the 960 series was in effect at publication. However, the May 2025 ruling is a direct legal precedent. US enterprises and non-US enterprises using US-origin software should treat expanded BIS coverage of the Ascend 960 as a credible future scenario and factor that into multi-year infrastructure procurement decisions.

Huawei's response to these concerns has been consistent across years of public statements: the company says it has never provided user data to any government and would not do so. That position is credible as an expression of corporate intent. It does not change what the National Intelligence Law requires.

What to Watch

Q4 2026: Ascend 950DT commercial shipments are expected to begin, powering DeepSeek's Inner Mongolia cluster and broader Chinese hyperscaler deployments. The volume Huawei can actually ship — given the CXMT HBM supply ceiling — will be the first real test of domestic supply chain sufficiency.

Q1 2027: Ascend 960DT is now scheduled for commercial availability. If the chip meets its announced timeline and performance claims, it will represent the first time Huawei's accelerated Tau Scaling Law cadence has held across a full generation transition. If the timeline slips or the performance doubling proves to be Huawei-reported rather than independently verified, the credibility of the 2028 and 2029 roadmap entries weakens accordingly.

OIF NPO standard: The 12.8 Tb/s NPO module Implementation Agreement that Huawei initiated at OIF Q2 2026 is still under development. How competing vendors — including those based in the US — implement NPO will determine whether Huawei's Hi-ONE architecture becomes the de facto standard or whether a competing implementation diverges from Huawei's design parameters. The September 10 NPO Standards Industry Summit reached consensus on development direction; the finalized specification publication will be the milestone to watch.

US cloud GPU controls: The US Commerce Department has reportedly been drafting rules that would block Chinese companies from remotely renting Nvidia compute in third-country data centers — expanding export-control scope from physical hardware to cloud API access. If enacted, this would close what Huawei's roadmap is already designed to not need: foreign cloud compute.

Frequently Asked Questions

When will the Huawei Ascend 960 be available, and who can buy it?

Huawei's rotating chairman David Wang announced at CONNECT 2026 that the Ascend 960DT — the training-optimized variant — is now scheduled for commercial availability in Q1 2027, three quarters earlier than the Q4 2027 timeline Huawei previously announced. The Ascend 960PR, optimized for prefill inference, will follow in Q3 2027. Both target deployment through Huawei Cloud China and partnerships with Chinese hyperscalers. For enterprises outside China: as of publication, no BIS ruling targets the Ascend 960 series specifically, but the May 2025 BIS ruling establishing that Ascend 910B, 910C, and 910D are prohibited for all persons globally is a direct precedent. Any enterprise considering Ascend 960 procurement should verify current BIS guidance before committing to infrastructure built on chips that may be prohibited before they ship commercially.

What is Near-Package Optics (NPO), and why does it matter for AI data centers?

NPO moves the optical engine from a pluggable front-panel slot in a switch to within approximately 5 centimeters of the accelerator chip itself, mounted on the PCB substrate near the ASIC. By shortening the electrical signal path, NPO eliminates the DSP retimer chips that traditional pluggable optical modules need to compensate for long-distance signal degradation — reducing both power consumption and latency. In Huawei's Ascend 960 SuperPoD, replacing 48,000 conventional 800G optical modules with 5,500 Hi-ONE NPO units cuts power consumption by over 550 kilowatts per cluster. The significance beyond hardware: Huawei initiated and won approval of the OIF's 12.8 Tb/s NPO project in May 2026 — making it both the architect of the technology and the initiator of the international standard that will govern it. NPO is projected to be part of a CPO/NPO market growing from approximately $100 million in 2025 to over $39 billion by 2030.

Does China's National Intelligence Law create a real risk for companies running AI workloads on Huawei's Ascend infrastructure?

Yes — the legal risk is structural and cannot be addressed by contract or server location. Article 7 of China's National Intelligence Law (2017) requires all Chinese organizations and citizens to cooperate with national intelligence work on demand. This obligation applies to Huawei regardless of whether its infrastructure is located in China, what its privacy policy says, or whether its customers are Chinese. Any AI workload — training data, inference queries, model weights, or processed outputs — running on Ascend-powered infrastructure operated by a Chinese entity is subject to this legal framework. The US has already sanctioned Huawei's prior Ascend chips (910B/C/D) under a ruling that applies to all persons globally. For regulated industries or enterprises handling sensitive data, the appropriate question is not "is the hardware technically capable?" but "is this legal framework compatible with our compliance obligations?"

How does Huawei's Ascend 960 compare to Nvidia's current chips?

No independent benchmarking data exists for the Ascend 960, which has not yet shipped. For context on its predecessor: DeepSeek's founder Liang Wenfeng stated in a July 2026 investor call that four Huawei GPUs are equivalent to one Nvidia GPU in effective compute, and that Huawei is approximately two years behind Nvidia in development. Spheron's independent analysis of the Ascend 950 found a 5.7x memory bandwidth gap between the 950's 4.0 TB/s and Nvidia's B200 at 8 TB/s — a gap that directly affects decode throughput in LLM inference at small batch sizes. Huawei's stated trajectory is to bring the Ascend 960 to rough parity with Nvidia's Blackwell architecture, and the Ascend 970 (2028) to parity with Nvidia's Rubin generation — which would represent the first time a Chinese AI chip has targeted performance parity with Nvidia's then-current rather than prior generation. Whether the timeline holds, and whether the performance figures prove out under independent measurement, are the two variables that matter most.