Dutch tech giant ASML's corporate headquarters in Veldhoven during its general shareholders' meeting on April 22, 2026. ASML, which makes cutting-edge machines to manufacture semiconductor chips, said on April 15, 2026 Freek VAN DEN BERGH/Getty Images

ASML Holding NV reported €9.3 billion in second-quarter net sales on Wednesday, raised its full-year 2026 revenue outlook to between €43 billion and €45 billion, and simultaneously announced the semiconductor industry's first commercial logic product manufactured using High-NA EUV lithography — a generational technology milestone that gives Intel Foundry a roughly three-year lead over TSMC in the most advanced chip-printing technology on earth. For investors, chip buyers, and AI infrastructure planners, the combined signal is clear: the AI-driven build-out of semiconductor manufacturing capacity is not a near-term blip, and the equipment needed to sustain it just crossed its next frontier.

The Dutch company also posted net income of €2.9 billion, earnings per share of €7.59, and a gross margin of 54.0% for the quarter ended June 28, 2026 — all above its own guidance and ahead of analyst consensus, according to ASML's Q2 2026 results.

Q2 Beat Driven by Strong Service Revenue

ASML's second-quarter total net sales of €9.3 billion climbed from €8.8 billion in the first quarter, lifted in part by higher-than-expected revenue from its Installed Base Management business — the service contracts and field upgrades it provides for machines already operating inside customer fabs. That segment contributed €2.8 billion in Q2, above guidance, and helped push gross margin from 53.0% in Q1 to 54.0% in Q2. ASML sold 86 new lithography systems in the quarter, up from 67 in Q1.

The company raised its full-year 2026 guidance to €43 billion–€45 billion in net sales, with a gross margin range of 54%–56% — a meaningful step up from its prior full-year guidance of €36 billion–€40 billion issued after Q1. For Q3 2026, ASML guided for net sales of €11.0 billion–€12.0 billion and a gross margin of 55%–57%, a significant sequential increase that implies second-half revenue acceleration, per ASML's Q2 2026 press release.

AI Demand Is Driving Every Signal ASML Can Measure

ASML was direct about the cause of its revenue and capacity momentum: AI. Artificial intelligence infrastructure investment, CEO Christophe Fouquet said in ASML's Q2 2026 earnings statement, is sustaining demand for advanced logic and memory chips from ASML's direct customers — TSMC, Samsung Foundry, and Intel Foundry — and those customers are accelerating their own capacity expansion plans in response.

"Ongoing AI-related investments and continued progress in AI technologies are driving demand for advanced Logic and Memory chips, further strengthening the semiconductor industry's growth outlook," Fouquet said. "Our customers, in turn, continue to accelerate their capacity expansion plans. This is translating into customer commitments across our product portfolio, providing ASML with increased visibility into longer-term demand."

That forward visibility is what makes ASML's order book the semiconductor industry's most reliable leading indicator. When ASML sees multi-year demand commitments from its three major foundry customers, it means TSMC, Samsung, and Intel have already made billion-dollar decisions about new fab capacity — decisions that typically take years to build and longer to pay off. The company's order intake, Fouquet said, remained extremely strong throughout the first half of the year.

Capacity Expansion Plans Stretch Through 2028

Based on the strength of that order intake, ASML announced plans to increase its production of EUV lithography systems by 30% for 2027 on top of its 2026 baseline — roughly 65 low-NA EUV systems per year. The company is also investigating a further 30% capacity increase for 2028. Importantly, the same scaling ambitions apply to its deep ultraviolet immersion lithography line, where 2026 capacity sits at approximately 130 systems annually, with a 30% expansion targeted for 2027 and another 30% under investigation for 2028.

These are not aspirational numbers. They represent capital commitments and operational investments that ASML's manufacturing and supply chain organizations have already begun executing against, per ASML's capacity expansion announcement. When a company with a near-monopoly position in its market signals capacity increases of this scale, the underlying demand signal has to be strong enough to justify multi-year capital risk — and ASML is signaling exactly that.

What High-NA EUV Is and Why the Panther Lake Milestone Matters

Alongside its earnings release, ASML announced that Intel Foundry has become the first company in the world to ship a high-volume logic product manufactured using High-NA EUV lithography. The product is a subset of Intel's Core Ultra Series 3 processors — code-named Panther Lake — built on Intel's most advanced 18A process node at the company's Fab D1X facility in Hillsboro, Oregon, per ASML's High-NA EUV production milestone announcement.

To understand why this milestone matters, it helps to understand what "High-NA" actually changes in a machine that already costs around $180 million per unit and weighs 180 to 200 tons.

Every EUV lithography system — ASML's standard NXE platform included — works by focusing 13.5-nanometer extreme ultraviolet light from a laser-pulsed tin plasma onto a semiconductor wafer. Because all matter absorbs EUV radiation, the entire optical system must operate in vacuum and use reflective mirrors rather than the transmissive lenses used in older lithography. The patterns etched by that light define the transistors and interconnects in a chip.

The "numerical aperture" of an optical system — abbreviated NA — determines the finest detail that system can resolve. ASML's standard EUV tools, the NXE platform, operate at a numerical aperture of 0.33. Its High-NA EUV platform, the EXE series, operates at 0.55 — a 67% increase in NA that enables proportionally finer patterning and denser transistor layouts without requiring the complex multi-patterning workarounds that dominate chip manufacturing today, as explained on ASML's EUV lithography technology page.

High-NA EUV: What the Extra Aperture Costs

The jump from 0.33 NA to 0.55 NA is not free. ASML's EXE series tools use what is called anamorphic optics — a 4×/8× demagnification system that shrinks features differently in two directions, rather than the symmetric 4× reduction of standard EUV. One engineering consequence of that geometry is a halved exposure field: where a standard EUV tool exposes a 26mm × 33mm area per shot, a High-NA tool covers only 26mm × 16.5mm. For large semiconductor die products — AI accelerators and many-core server chips that span the full exposure field — this means every layer that uses High-NA EUV requires two exposures stitched together, a process called half-field stitching, adding process complexity and cost.

The depth of focus also shrinks dramatically at higher numerical aperture, falling to roughly one-third of what is achievable on standard EUV tools. That requires resist layers thinner than 30 nanometers, which in turn makes the patterning process more vulnerable to photon shot noise and stochastic defects — random variations in where photons land that can cause bridging or missing features at the smallest geometries.

There is also a direct cost differential: a single High-NA EUV exposure costs approximately 2.5 times more than a Low-NA EUV exposure, and the tool itself — ASML's TWINSCAN EXE series — is priced at around $380 million to $400 million per unit, roughly double the cost of a standard EUV system. These constraints explain why Intel is using High-NA EUV on select layers of Panther Lake rather than the entire chip, and why the Panther Lake production layers are also dual-qualified on Intel's existing standard EUV fleet, with yields "matched to the NXE platform," as the ASML press release states. The cost differential is confirmed by independent cost analysis of High-NA EUV exposures.

The second-generation EXE:5200B, which Intel was the first to install and pass acceptance testing for, in late 2025, improves on the original EXE:5000 with a higher-power EUV light source, improved throughput of approximately 175 wafers per hour, and overlay accuracy of 0.7 nanometers. In February 2026, ASML confirmed that its High-NA EUV tools had processed over 500,000 wafers at roughly 80% uptime — a benchmark that formally cleared the path from research tool to production platform, per ASML's February 2026 HVM readiness announcement.

Intel's Foundry Edge Over TSMC — and Why It Has a Shelf Life

The most strategically significant dimension of today's announcement is not what Intel did, but what TSMC has chosen not to do. TSMC, the world's dominant advanced logic foundry, has publicly stated it will skip High-NA EUV for its initial A14 (1.4nm) process node, opting instead to push standard EUV tools to their performance limits through advanced multi-patterning. Industry analysts expect TSMC to begin High-NA EUV adoption around 2029, based on TSMC's own public statements on its High-NA EUV strategy.

That gap — Intel in production today, TSMC in production approximately three years from now — represents an unusual inversion of the foundry competitive order. TSMC has outpaced Intel in process node leadership for years; on High-NA EUV, Intel Foundry carries the first-mover advantage. Naga Chandrasekaran, Intel Foundry's Executive Vice President and General Manager, acknowledged the significance on Wednesday.

"By qualifying the High NA EUV process option on select Intel 18A product layers, our existing fleet of tools are providing customers with increased output, while we develop future options to achieve leading-edge performance, density and manufacturing flexibility on upcoming nodes," Chandrasekaran said in ASML's High-NA milestone announcement.

Samsung sits between the two. The South Korean company secured its own EXE:5200B systems earlier in 2026 and is targeting High-NA EUV for its 2nm SF2 process and sub-2nm logic nodes, as well as for HBM4 advanced memory production, per reports on Samsung's High-NA EUV adoption plans. Intel's lead is real but contested.

The practical question for Intel Foundry's customers — and for the hyperscalers commissioning next-generation AI accelerators — is whether Intel can sustain commercially viable yields at the 18A node using High-NA EUV before TSMC closes the gap. Intel's 14A process, which will use High-NA EUV more extensively, is expected to enter risk production in late 2026 or early 2027, with high-volume manufacturing targeted for 2028, per Intel's 14A process roadmap.

What This Means for Anyone Depending on Advanced Chips

ASML's position in the supply chain means its signals propagate outward. A confirmed guidance raise to €43 billion–€45 billion in annual revenue, paired with binding capacity expansion commitments through 2028, tells the rest of the semiconductor ecosystem that ASML's largest customers — the three foundries that collectively manufacture every advanced AI chip on earth — have made firm capital commitments to expand fab capacity at a pace that justifies double-digit ASML revenue growth for at least the next two years.

For AI infrastructure operators at Microsoft, Google, Amazon, and Meta, that is direct evidence that the physical substrate of AI computing is being built out on a multi-year timeline, not a short cycle. The hyperscalers' GPU and accelerator orders flow to TSMC and Intel Foundry; those foundry commitments flow to ASML. When ASML raises guidance and locks in capacity for 2027 and 2028, it is reflecting demand signals that were set in motion at the hyperscaler level twelve to eighteen months ago.

ASML repurchased approximately €1.1 billion in shares during Q2 under its 2026–2028 buyback program and declared an interim dividend of €1.88 per ordinary share, payable August 5, 2026, per ASML's Q2 2026 capital return announcement. The company's next Capital Markets Day is scheduled for June 10, 2027, at which point Fouquet said ASML will update its longer-term financial and strategic outlook.

"With increased resolution and better process control, the introduction of High NA EUV marks a substantial development in semiconductor lithography," Fouquet said in ASML's High-NA EUV milestone release. "We are proud to play a role in enabling the smaller, denser patterning that will accelerate advancements in AI and other emerging technologies."

The next frontier is already visible. ASML has announced development of a Hyper-NA EUV platform with numerical aperture above 0.55 — potentially as high as 0.75 or 0.85 — expected to be available around 2030, at an estimated price of approximately $720 million per tool. Before then, China's domestically developed EUV prototype, reported by Reuters in December 2025, is expected to produce its first working chips between 2028 and 2030. Whether it succeeds determines whether ASML's monopoly on the world's most consequential manufacturing technology remains as total as it is today.

Frequently Asked Questions

What is High-NA EUV lithography and why does it matter for chip manufacturing?

High-NA EUV (High Numerical Aperture Extreme Ultraviolet) lithography is the next generation of chip-printing technology beyond the standard EUV machines that have been used in volume production since 2019. The key difference is the optical aperture: ASML's standard EUV tools use a numerical aperture of 0.33; the High-NA EXE platform raises that to 0.55, enabling proportionally finer features on a chip. That higher resolution is what makes sub-2nm semiconductor nodes economically possible without stacking four or five complex multi-patterning exposures per layer. It matters because chips at these geometries — in AI accelerators, advanced memory, and next-generation processors — require more transistors packed more densely than standard EUV can achieve in a single exposure. Intel Foundry's Panther Lake product, announced Wednesday, is the first commercial logic chip manufactured using this technology.

Will TSMC adopt High-NA EUV, and if so, when?

TSMC has publicly stated it plans to skip High-NA EUV for its initial A14 (1.4nm) process node, choosing instead to extend standard EUV tools through advanced multi-patterning. Industry analysts and foundry observers expect TSMC to begin High-NA EUV adoption around 2029. That decision is primarily economic: each High-NA EUV exposure costs approximately 2.5 times more than a standard EUV exposure, and the tool itself costs roughly double. At TSMC's production scale, the cost-per-wafer math currently does not favor High-NA for its first sub-2nm generation. Samsung, by contrast, has secured its own High-NA EXE:5200B systems and is targeting the technology for its 2nm SF2 process in 2026.

What does ASML's raised 2026 guidance tell AI infrastructure investors?

ASML's decision to raise its full-year 2026 revenue guidance from a prior range of €36 billion–€40 billion to €43 billion–€45 billion reflects binding customer commitments across its product portfolio — commitments that TSMC, Samsung, and Intel make one to two years before they show up in fab output or GPU availability. When ASML raises guidance and simultaneously locks in +30% capacity expansions for 2027 and 2028, it is confirming that the hyperscalers (Microsoft, Google, Amazon, Meta) made multi-billion-dollar AI infrastructure decisions that are now propagating through the supply chain. For investors tracking AI hardware demand, ASML's order book is the earliest and most reliable forward signal available — more current than any chipmaker's earnings call and more specific than any macro forecast.

Why does a High-NA EUV exposure cost 2.5 times more than a standard EUV exposure?

The cost premium comes from two engineering tradeoffs built into the higher numerical aperture. First, the optical geometry — anamorphic 4×/8× demagnification versus the symmetric 4× in standard EUV — produces a smaller exposure field (26mm × 16.5mm instead of 26mm × 33mm), which means the same die area requires more shots, or half-field stitching, adding process steps. Second, the 0.55 NA dramatically reduces depth of focus (to about one-third of standard EUV), requiring thinner photoresist layers that must absorb the same photon dose over a shorter depth, demanding more precise process control and slower throughput at equivalent yield targets. The tool cost — roughly $380 million to $400 million per unit versus approximately $180 million for a standard EUV scanner — also contributes to higher amortized cost per wafer pass. Together, these constraints are why Intel is initially qualifying High-NA EUV on select chip layers rather than the full process stack.