Intel Foundry became the first chipmaker in history to ship a high-volume logic product manufactured using High-NA EUV lithography, ASML and Intel announced Wednesday as ASML reported its Q2 2026 earnings — a milestone that puts Intel years ahead of TSMC, which has confirmed it will not deploy the same technology in production until at least 2029.

The chips in question are a subset of Intel's Core Ultra Series 3 processors, codenamed Panther Lake and built on the Intel 18A process node. Specific patterning layers of these already-shipping consumer laptop chips are now produced on ASML's EXE:5000 High-NA EUV scanner at Intel's Hillsboro, Oregon fab, with yields matched to Intel's existing standard-EUV production line. ASML's joint announcement with Intel coincided with Q2 2026 results showing €9.3 billion in net sales and €2.9 billion in net income, with the company raising its full-year 2026 revenue outlook to between €43 billion and €45 billion.

High-NA EUV vs. Standard EUV: What the Optical Upgrade Actually Changes

Standard EUV lithography — the technology already used by TSMC, Samsung, and Intel for several generations of chips — operates at a numerical aperture of 0.33. ASML's High-NA tools push that to 0.55, a change that directly governs how fine a circuit pattern the scanner can resolve in a single exposure. The higher the numerical aperture, the smaller the features that can be printed without resorting to multi-pass patterning.

In practical terms, the jump from 0.33 NA to 0.55 NA brings the single-exposure feature resolution from roughly 13 nanometers into sub-10 nanometer territory — a gain that matters most for the densest metal and contact layers inside a leading-edge logic chip, where transistors are packed at their tightest pitch. Rather than printing those critical layers in two separate passes using the existing tool fleet, a chipmaker using High-NA can potentially achieve the same or finer result in one.

That improvement carries a significant engineering cost. The EXE:5000 scanner weighs roughly 165 tons, requires an EUV light source producing at least 500 watts of output power (compared to 250 watts for the current generation), and costs approximately $400 million per unit — roughly double the price of a standard 0.33 NA EUV tool. The optics system also uses an anamorphic 4×/8× magnification design, different in one axis from the 4× isomorphic system used in 0.33 NA tools. That anamorphic design is what achieves the higher resolution, but it also cuts the exposure field size in half — to 26 × 16.5 millimeters from 26 × 33 millimeters — which means a die larger than that field requires two stitched exposures rather than one. For Intel's Panther Lake, which is itself a multi-tile design with a compute tile measuring roughly 115 mm², the reduced field is not a production constraint. For a hypothetical large monolithic AI accelerator die, it would be.

Intel is not running High-NA EUV across all 18A layers. Specific layers are now "dual-qualified" — meaning the process is validated to run on either the High-NA scanner or the existing standard-EUV NXE tools interchangeably. The primary purpose of this selective deployment, as Intel and ASML both note, is to gather production data on system setup, uptime, and manufacturing implementation before committing more layers to the new platform.

Why Panther Lake's 18A Architecture Makes This Milestone Possible

Panther Lake is the first Intel consumer CPU built entirely on the 18A process node — and that process node represents Intel's most significant architectural change in over a decade. Two advances define it.

The first is RibbonFET, Intel's implementation of gate-all-around transistors. In the previous FinFET architecture that has dominated semiconductor manufacturing since the early 2010s, the gate — the structure that controls current flow through the transistor — contacts the silicon channel on three sides. In RibbonFET, the gate wraps entirely around stacked horizontal nanosheets, touching the channel on all four sides. That additional contact improves electrostatic control, reduces leakage current, and allows the transistor to switch at lower voltages without sacrificing drive current. Intel reports that RibbonFET on 18A delivers up to 15% better performance per watt compared to the prior Intel 3 node's FinFET design.

The second is PowerVia, Intel's backside power delivery network. In a conventional chip, the metal layers that carry power and the metal layers that carry signals compete for space on the same front side of the wafer. PowerVia moves the power delivery network to the back of the silicon, routing current through nano-scale through-silicon vias to reach the transistors. This eliminates the front-side congestion, reduces the resistance of power wires, and cuts dynamic voltage droop — the momentary voltage sag that limits how fast a processor can run. At Intel's VLSI Symposium presentation in June 2026, the company reported that PowerVia on 18A delivers a tenfold reduction in dynamic voltage droop and enables up to 6% higher operating frequency versus a comparable front-side interconnect design. Intel also reported an 11% reduction in routed wiring area.

Together, RibbonFET and PowerVia give Intel 18A a combination that neither TSMC's N2 node nor Samsung's SF2 currently offers in the same generation — particularly on backside power delivery, where TSMC has indicated it is still developing its own implementation for future nodes. The Panther Lake dies that are now being patterned on High-NA EUV inherit both advances.

Intel First, TSMC Later: What the Foundry Gap Means

The competitive significance of Wednesday's announcement lies not just in what Intel has done, but in when TSMC and Samsung plan to follow.

TSMC, the world's dominant contract chipmaker and ASML's largest EUV customer, does not plan to use High-NA EUV in production for any chip node through 2029. At its North America Technology Symposium in April 2026, TSMC Deputy Co-COO Kevin Zhang confirmed the company's roadmap through its A13 and A12 nodes — both planned for 2029 — relies entirely on conventional Low-NA EUV tools running advanced multi-patterning techniques. Zhang described the High-NA tools as "very, very expensive," with units now priced above €350 million each. TSMC has purchased a small number of High-NA EUV systems for research and development, but has explicitly ruled out production deployment before 2029.

TSMC's multi-patterning approach is not a concession — it is a deliberate engineering judgment. By printing the same circuit layer in multiple passes with existing 0.33 NA tools, TSMC can achieve comparable or finer final resolution at lower capital cost per wafer. The tradeoff is process complexity: each additional patterning step introduces alignment error and increases cycle time. Whether TSMC's multi-pass approach holds cost and quality parity with Intel's single-pass High-NA approach at the tightest pitches remains an active engineering debate, and TSMC's willingness to defer is a statement of confidence in its own integration capability.

Samsung Foundry is taking a different position. The company has already installed ASML's High-NA EUV system at its NRD-K advanced research facility and has confirmed it will use the tool on selected layers of its SF1.4 process, targeted for mass production in 2029 — one to two years later than Samsung originally planned due to yield challenges on its 2nm SF2 node. Samsung expects ASML to deliver approximately seven High-NA EUV systems by the end of 2027 in preparation for that ramp.

That positioning makes Intel, for the foreseeable future, the only logic foundry running High-NA EUV at production scale. "With increased resolution and better process control, the introduction of High NA EUV marks a substantial development in semiconductor lithography," ASML President and CEO Christophe Fouquet said in the joint release. "We are proud to play a role in enabling the smaller, denser patterning that will accelerate advancements in AI and other emerging technologies."

What This Does — and Does Not — Mean for Intel's 14A Roadmap

Intel and ASML are careful to frame Wednesday's announcement as a milestone in an adoption curve, not the full deployment of High-NA EUV across its process portfolio. The technology is currently running on selected 18A layers for the purpose of collecting data — system uptime, setup efficiency, manufacturing consistency — that will inform broader integration decisions. Further incorporation into additional nodes, both companies note, will depend on customer requirements and continued technical refinement.

The larger opportunity lies with Intel's 14A process — the successor to 18A — which Intel has described in public statements and SEC filings as designed to incorporate High-NA EUV on additional layers, with risk production targeted in approximately 2027–2028 and high-volume manufacturing expected around 2029. Tesla signed on as the first publicly confirmed 14A customer in April 2026. Intel is also in early evaluation stages with Nvidia for a future GPU architecture and has reportedly committed to manufacture more than three million Google TPU units in 2028, though neither the Nvidia nor Google engagements have been officially confirmed at committed production volumes.

"By qualifying the High NA EUV process option on select Intel 18A product layers, our existing fleet of tools are providing customers with increased output, while we develop future options to achieve leading-edge performance, density and manufacturing flexibility on upcoming nodes," said Intel Foundry Executive Vice President and General Manager Naga Chandrasekaran.

The production data that flows from today's Panther Lake High-NA runs is expected to directly accelerate Intel and ASML's readiness to deploy the technology more extensively on 14A — making the Panther Lake milestone valuable not only as a symbolic first but as an engineering test bed for the more consequential ramp ahead.

ASML, for its part, has plans to expand its High-NA EUV manufacturing capacity. The company has outlined intentions to increase High-NA output by approximately 30% for 2027 in anticipation of accelerating demand from Intel and Samsung as their leading-edge roadmaps mature — though ASML has not confirmed that figure in Wednesday's earnings release, and its realization will depend on customer commitments and production ramp timelines.

ASML's Earnings: High-NA Gains Credibility at a Critical Moment

The timing of the Intel announcement matters for ASML's own investor narrative. TSMC's April confirmation that it would not use High-NA EUV in production through 2029 sent ASML's shares down roughly 3% intraday, erasing approximately €14 billion in market value, as investors recalculated near-term High-NA demand. Intel's production milestone — chips shipping to customers, patterned in part on the $400 million tools ASML's skeptics wondered about — is the most direct counter to that concern: the technology is production-ready, not a lab prototype waiting for a customer.

ASML's Q2 2026 results, reported Wednesday alongside the Intel announcement, showed €9.3 billion in total net sales and €2.9 billion in net income, both above guidance. The company raised its full-year 2026 revenue outlook to between €43 billion and €45 billion, with gross margins projected at 54–56%. The earnings context reinforces that ASML's business does not depend on High-NA EUV adoption alone — its installed base of NXE standard-EUV and DUV immersion tools generates substantial service revenue — but the Intel milestone removes one of the most persistent questions about whether High-NA EUV could achieve real-world production quality.

For a technology that MIT Technology Review once called "the machine that saved Moore's Law," ASML's standard EUV tools spent years being described as impossible before they became indispensable. High-NA EUV is following a shorter version of the same trajectory.

Frequently Asked Questions

What makes High-NA EUV different from the EUV already used by Intel, TSMC, and Samsung?

Standard EUV tools — the kind already in production at all three foundries — operate at a numerical aperture of 0.33, which governs how finely the scanner can resolve circuit features in a single exposure. ASML's High-NA tools push the numerical aperture to 0.55, enabling sub-10 nanometer feature resolution compared to roughly 13 nanometers for existing tools. The higher aperture comes at significant cost: at approximately $400 million per unit, a High-NA EUV scanner costs roughly double a standard EUV tool and requires substantially more engineering infrastructure. Intel is currently using High-NA EUV on specific selected layers of its 18A process, with remaining layers handled by its existing standard EUV fleet. For the full technical breakdown, see the ASML EXE:5000 product page.

Does High-NA EUV work equally well for all chip designs?

No — and this is a constraint the announcement does not highlight. ASML's High-NA scanners use an anamorphic optical design that halves the exposure field size to 26 × 16.5 millimeters, compared to the 26 × 33 millimeter field of standard 0.33 NA tools. A chip die that is larger than this reduced field must be patterned using two stitched exposures rather than one. Intel's Panther Lake, a multi-tile design in which the compute die measures roughly 115 mm², fits comfortably within the High-NA field. Larger future products — particularly high-end AI accelerators designed as big monolithic dies — would face additional complexity when patterned on High-NA EUV, which reinforces the industry-wide push toward chiplet and tile architectures as the natural design approach for the High-NA era. Intel's official breakdown of Panther Lake architecture details covers the multi-tile approach in full.

When will consumers actually see chips that use High-NA EUV?

They already can. Intel's Core Ultra Series 3 processors — Panther Lake — are the world's first logic chips partially manufactured using High-NA EUV, and they are currently shipping in laptops and, as of July 2026, in industrial Mini-ITX systems such as the COMMELL LV-6718. Not every layer of every Panther Lake chip uses High-NA EUV — Intel is applying the technology selectively to specific 18A layers — but the chips are in the market. The broader consumer impact will grow as Intel's 14A process, planned for high-volume manufacturing around 2029, is designed to use High-NA EUV on additional layers. That is also roughly when Samsung plans to use High-NA EUV in its own SF1.4 process — and still when TSMC says it will not. Details on the Intel Core Ultra Series 3 launch are available from Intel's CES 2026 announcement.

Why is TSMC not using High-NA EUV if it delivers better resolution?

TSMC's position, confirmed by Deputy Co-COO Kevin Zhang at its North America Technology Symposium in April 2026, is that multi-patterning — printing critical layers in two passes using the existing 0.33 NA EUV fleet — can achieve comparable resolution at lower capital cost per wafer. Each High-NA EUV scanner costs more than €350 million, and TSMC's scale makes the cumulative investment enormous. The company's own R&D teams have found ways to continue scaling its A13 and A12 nodes through 2029 without requiring the new tools. That said, TSMC has purchased a small number of High-NA systems for research purposes, and most analysts expect it will adopt the technology for production after 2029, when multi-patterning yields diminish at tighter pitches. Intel's first-mover position means it will have roughly three years of production experience on High-NA EUV before TSMC begins mass production. Tom's Hardware has a detailed breakdown of TSMC's 2029 High-NA EUV stance.