Hamburg's Congress Center (CCH) opens its doors today to the global high-performance computing community as ISC High Performance 2026 begins its five-day run through June 26. Now in its 41st year, ISC remains Europe's oldest and most-attended gathering for HPC, AI, and quantum computing — and this edition arrives at a genuine inflection point: the first generation of exascale machines is operational, GPU-accelerated AI workloads are competing for the same infrastructure as scientific simulation, and energy has become a first-class design constraint rather than an afterthought. As of last week, 3,474 attendees had registered, and 188 exhibitors from 26 countries — including 44 organizations exhibiting at ISC for the first time — will fill the CCH floor through Thursday.

This year's theme, "Connecting the Dots," reflects a deliberate shift in how the community frames progress: not as isolated advances in raw compute or AI acceleration, but as the convergence of HPC, AI, quantum, and cloud into tightly coupled workflows constrained by real-world power and cost. At the center of that frame is an open-source software infrastructure — tools like Spack, Kokkos, Flux, and Slurm — that has quietly become the connective tissue making heterogeneous hardware usable at scale. Jülich Supercomputing Centre (JSC) is celebrating JUPITER, Europe's first exascale supercomputer, at its dedicated booth this week — a milestone that gives the European HPC community its own proof point in the post-Moore era and reshapes what "Connecting the Dots" means in practice.

Day One: Tutorials Open Today

Today's program features 23 full-day and half-day tutorials — the largest tutorial program ISC has offered, many with hands-on components. Sessions span efficient distributed GPU programming for exascale workloads, hybrid quantum-classical workflows, AI methods in scientific computing, performance optimization, reproducibility, and the European Environment for Scientific Software Installations (EESSI). JSC is a major contributor: Andreas Herten leads the "Efficient Distributed GPU Programming for Exascale" tutorial, and Sebastian Achilles leads the EESSI introduction session. Tutorial passes are available at a new reduced price this year, a deliberate move to broaden access beyond well-resourced institutions.

Post-Moore Era Opens the Keynote Stage

The main conference program begins Tuesday morning with an opening keynote from Prof. Dr. Martin Schulz, Chair of Computer Architecture and Parallel Systems at the Technical University of Munich and a board member of the Leibniz Supercomputing Centre. The framing is direct: Moore's Law and Dennard Scaling — the paired forces that delivered predictable performance and power improvements for half a century — have effectively plateaued, and the HPC community now faces bottlenecks in data movement, memory bandwidth, and energy efficiency that incremental GPU improvements alone cannot resolve. His talk will address what transformative architectural innovation looks like in this environment, including the role of quantum technologies integrated alongside classical supercomputing systems.

This framing matters beyond the opening session. The practical consequence of the post-Moore plateau is that performance gains now require co-design — hardware, software, and application teams working together rather than waiting for the next process node. That is precisely the problem the High Performance Software Foundation (HPSF) exists to address.

Open-Source Software Becomes HPC's Load-Bearing Layer

One of the most significant institutional developments at ISC 2026 is the expanded presence of the HPSF, the Linux Foundation project launched at ISC 2024 to build, promote, and advance a portable, open-source core software stack for HPC. Its membership spans Amazon Web Services, HPE, Lawrence Livermore National Laboratory, Sandia National Laboratories, AMD, Argonne, Intel, Kitware, Los Alamos, NVIDIA, and Oak Ridge National Laboratory.

The HPSF's trajectory over the past year has been significant. HPSFCon 2026 was held in Chicago in March, bringing together maintainers of projects including Spack (the HPC package manager), Kokkos (a performance-portable C++ programming model), Flux Framework, HPX (a C++ parallel and distributed computing framework that joined HPSF as an established project before ISC), Apptainer, Chapel, Charliecloud, AMReX, Trilinos, and WarpX. This week, HPSF is convening community members at ISC to discuss the future of open-source infrastructure for the post-Moore, AI-accelerated HPC era. A co-located HPSF minisymposium at the PASC conference will focus specifically on addressing the growing complexity of modern hardware and building sustainable, portable software for the future of HPC.

The significance of this software layer is concrete, not abstract. When a new hardware architecture enters an HPC center — a different GPU, an AI accelerator, a RISC-V node, or a quantum co-processor — the question of whether existing scientific applications can run on it without a complete rewrite is answered by tools like Kokkos and Spack. Portability is not a convenience feature at this scale; it is what makes hardware diversity economically viable for national laboratories and research institutions operating on fixed budgets.

NVIDIA Vera Rubin NVL72: What the New Rack Architecture Means for HPC

NVIDIA's presence at ISC 2026 centers on the Vera Rubin NVL72, the company's rack-scale successor to the GB200 NVL72 that integrates 72 Rubin GPUs and 36 Vera CPUs into a single system connected by the sixth-generation NVLink 6 fabric. The architecture delivers 260 TB/s of all-to-all fabric bandwidth — double the 130 TB/s of its predecessor — along with 3.6 exaflops of NVFP4 inference throughput. Each Rubin GPU carries 288 GB of HBM4 memory at up to 22 TB/s of bandwidth, compared to 8 TB/s for HBM3e in the previous Blackwell generation. The Vera CPU pairs 88 custom Olympus Arm cores with 1.8 TB/s of NVLink chip-to-chip coherent bandwidth — connecting CPU and GPU resources under a single fabric domain for the first time in a rack-scale commercial system.

HPE (booth C10) is featuring the Vera Rubin NVL72 as its flagship leadership-class offering at ISC, with VP Jim Luján presenting the system to the conference audience. NVIDIA announced the Vera Rubin platform at CES 2026 in January and confirmed it entered full production in Q1 2026; partner availability at cloud providers including AWS, Google Cloud, Microsoft Azure, and CoreWeave is scheduled for the second half of 2026. CoreWeave completed the first full system-level validation of a Vera Rubin NVL72 rack on June 1, 2026.

For HPC practitioners, the Vera Rubin NVL72 raises immediate practical questions. The transition from NVLink 5 to NVLink 6, the new Vera CPU architecture, and the shift to HBM4 all require updates across the Spack build system, the Kokkos performance portability layer, and MPI and OpenMP runtime configurations. These are live engineering questions for HPSF project communities, and ISC is where much of that discussion will take shape this week.

Vascular Digital Twins: Wednesday's Medical Supercomputing Keynote

Wednesday's keynote comes from Dr. Amanda Randles, Associate Professor of Biomedical Sciences and Biomedical Engineering at Duke University and Director of the Duke Center for Computational and Digital Health Innovation. Her talk, "HPC for Vascular Digital Twins," will demonstrate how GPU-accelerated supercomputing and extreme-scale parallelism are enabling medicine to move from static imaging snapshots to time-evolving simulations of human physiology — models tracking thousands to millions of cardiac cycles, integrating wearable sensor streams, and enabling early cardiovascular risk assessment. The session will be facilitated by Women in HPC (WHPC), continuing ISC's formal partnership with the organization across research sessions, panels, and facilitated discussions this year.

The Full Technical Program: Six Track Areas

The three-day conference and exhibition program, which opens Tuesday, covers six track areas that reflect the hardware-software tensions practitioners are actively navigating.

Systems Architecture and Memory addresses the von Neumann bottleneck directly, with the "Advanced Memory Architecture" panel covering memristors, in-memory computing, and memory disaggregation. A separate "On-Chip Networks" session brings chiplet-based processor designers together to examine interconnection at rack and data center scale.

AI and HPC Infrastructure defines what "AI-ready infrastructure" means in operational terms — fabric choices, job scheduling, storage I/O, and energy constraints. Sessions will address the memory wall as AI training scales, confidential computing at supercomputing scale, and the design of AI factories within real power grid limits.

Quantum Computing and HPC frames classical HPC as an enabler of quantum computing rather than its eventual successor. The panel "HPC-Enabled Path to Using, Scaling, and Operating QC" will examine how supercomputers support quantum error correction (QEC) decoding, emulation, scheduling, and control for near-term quantum devices.

Weather and Climate at Exascale highlights teams running kilometer-scale atmospheric and ocean models — resolutions previously considered infeasible — using exascale infrastructure.

Energy Efficiency and Diversity in HPC combines technical talks on sustainable computing with a deliberate focus on early-career researchers and underrepresented communities in the field.

Software Stacks and Security addresses pressure on software stacks to support new programming languages, AI-heavy mixed workloads, and confidential computing across CPU, GPU, and high-speed interconnects.

Is RISC-V Ready for Production HPC?

Friday's workshop program includes the fifth annual International Workshop on RISC-V for HPC at ISC, organized by Daniel Seibel and Prateek Chawla of JSC. The workshop has tracked RISC-V server-class silicon development since the architecture emerged from research labs into commercial chipmaking. The central question remains unresolved: RISC-V has produced meaningful server-class silicon — including chips tracking the performance trajectory of established x86-64 and Arm processors at the benchmark level — but commercial production HPC deployments at major Western cloud providers and national laboratories do not yet exist.

One data point the HPC community is watching is the trajectory of the Sophon SG2044, a 64-core RISC-V server processor from SOPHGO. Researchers evaluating RISC-V hardware from Chinese manufacturers should note that SOPHGO was added to the U.S. Department of Commerce Bureau of Industry and Security (BIS) Entity List on January 16, 2025, for activities BIS described as advancing China's indigenous advanced chip production in ways contrary to U.S. national security interests. This designation prohibits U.S. companies from supplying SOPHGO without a license and is a material factor for any institution assessing supply chain risk in RISC-V hardware procurement.

Friday's workshop will address compiler support for the RISC-V Vector extension (RVV), performance on HPC benchmarks, and the realistic trajectory toward RISC-V in production HPC clusters.

The Exhibition, Research Posters, and the Dongarra Award

The ISC 2026 exhibition opens Tuesday at 1:00 pm and runs through Thursday at 4:00 pm. Beyond NVIDIA and HPE, the floor includes the Gauss Centre for Supercomputing (GCS) at booth K02, where Jülich Supercomputing Centre, High-Performance Computing Center Stuttgart (HLRS), and Leibniz Supercomputing Centre are co-represented. JSC's dedicated JUPITER booth showcases Europe's first exascale supercomputer, a machine hosted at JSC in Jülich, Germany.

Three research poster finalists illustrate the week's technical breadth. A poster from HLRS examines sparse matrix-vector multiplication on the Cerebras wafer-scale engine — specifically where communication bottlenecks limit throughput when a classic HPC workload meets an AI-specialized architecture. A poster from Brightskies Inc. presents HADEER, a hybrid AI-driven framework for reservoir modeling and production optimization in the energy sector. A poster from Ohio State University addresses NIMBLE, a multi-path balancing approach for GPU cluster fabric efficiency as training and inference workloads scale. All research papers presented at ISC 2026 will be published open access in IEEE Xplore, with ISC covering publication costs.

The 2026 Jack Dongarra Early Career Award has been awarded to Devesh Tiwari of Northeastern University for contributions to sustainable high-performance computing and post-Moore computing systems, including hybrid quantum-classical HPC.

What ISC 2026 Signals for the Field

ISC 2026 arrives as several converging trends demand simultaneous responses. The first generation of true exascale machines is operational — Frontier in the United States, JUPITER in Europe. GPU-accelerated AI workloads have moved from research demonstrations to production HPC infrastructure, creating scheduling, power, and storage challenges that ISC's program directly addresses. The HPSF software layer — Spack, Kokkos, Flux, Slurm, and affiliated projects — has matured from individual tools into governed infrastructure, analogous to what the Cloud Native Computing Foundation (CNCF) did for cloud-native software a decade ago.

The two hardware questions the open-source runtime and compiler communities will be watching most closely as the week unfolds are how the NVIDIA Vera CPU's NVLink 6 architecture propagates through existing HPC software stacks, and how close RISC-V server hardware is to the performance threshold needed for production deployment — with the caveat that at least one prominent manufacturer of RISC-V HPC-targeted silicon, SOPHGO, operates under U.S. export controls that limit its integration into Western supply chains.

ISC High Performance 2026 runs through Friday, June 26, 2026, at the Congress Center Hamburg (CCH), Congressplatz 1, Hamburg, Germany.

Frequently Asked Questions

What is ISC High Performance and why does it matter for HPC practitioners?

ISC High Performance, founded in 1986 as the Mannheim Supercomputer Seminar, is the world's oldest supercomputing conference and Europe's largest annual gathering for HPC, AI, and quantum computing. For practitioners, it is the primary venue where hardware vendors, national laboratories, and open-source maintainers converge to address the engineering challenges of large-scale computing — including software portability across heterogeneous hardware, energy efficiency, and the integration of quantum co-processors alongside classical HPC infrastructure. The 2026 edition is the 41st and opens today in Hamburg.

What is the High Performance Software Foundation and how does it relate to open-source HPC tools like Spack and Kokkos?

The High Performance Software Foundation (HPSF) is a Linux Foundation project launched at ISC 2024 that provides neutral governance and development support for the open-source tools underpinning HPC software stacks worldwide. Its portfolio includes Spack (the HPC package manager used to build scientific software across heterogeneous hardware), Kokkos (a C++ performance portability layer enabling code to run on CPUs, GPUs, and other accelerators without full rewrites), Flux Framework, Apptainer, HPX, Charliecloud, and others. HPSF's significance is that it addresses the software sustainability problem that post-Moore hardware diversity creates: as architectures fragment, the cost of maintaining portable scientific applications on proprietary toolchains becomes prohibitive for national laboratories and research institutions.

What are the technical differences between the NVIDIA Vera Rubin NVL72 and its predecessor, and why do they matter for HPC?

The Vera Rubin NVL72 moves from NVLink 5 to NVLink 6 at 260 TB/s all-to-all fabric bandwidth — double the 130 TB/s of its predecessor — and from HBM3e to HBM4 memory, increasing per-GPU bandwidth from 8 TB/s to 22 TB/s. The 72 Rubin GPUs and 36 Vera CPUs are connected under a single coherent fabric domain, the first rack-scale architecture to unify CPU and GPU resources this way. For HPC workloads, data movement between CPU-resident data structures and GPU compute no longer crosses a PCIe boundary, enabling tighter coupling of preprocessing, simulation, and post-processing pipelines within a single rack. The practical implication for the open-source HPC stack is that Spack, Kokkos, and MPI/OpenMP runtimes all require updates to take full advantage of the new architecture.

Is RISC-V ready for production HPC deployment, and what are the current barriers?

As of mid-2026, RISC-V server-class silicon has made meaningful progress in compute and memory bandwidth benchmarks, but commercial production deployments at U.S. cloud providers and national laboratories do not yet exist. Barriers include compiler maturity for the RISC-V Vector extension (RVV), ecosystem tooling gaps relative to x86-64 and Arm, and supply chain considerations. The most prominent current RISC-V server-class chip manufacturer with HPC-targeted silicon, SOPHGO, was added to the U.S. BIS Entity List in January 2025, limiting its integration into Western HPC supply chains. The RISC-V for HPC workshop at ISC 2026 on Friday will address these gaps directly.