A pioneering research team, led by Professor Hu Yizhe from the School of Microelectronics at the University of Science and Technology of China (USTC), has accomplished a groundbreaking advancement in the realm of Phase-Locked Loop (PLL) chip research. Leveraging an innovative "charge-steering sampling technology," the team has devised a state-of-the-art, all-digital PLL architecture that operates seamlessly in both integer and fractional charge domains, boasting an impressive jitter performance of approximately 60 femtoseconds (fs). This technology effectively addresses the shortcomings of traditional PLL analog filters, such as their large footprint and limited sampling isolation.

The innovative approach employs high phase detection gain to mitigate in-band quantization noise, thereby enhancing loop bandwidth to reduce the phase noise of digitally controlled oscillators. Additionally, it utilizes multi-bit digital phase output to significantly improve locking speed and robustness. These remarkable achievements have been published in the prestigious IEEE Journal of Solid-State Circuits, garnering widespread acclaim and interest within the academic and industry circles.