The research team, led by Liu Xinyu and Zheng Xuqiang from the High Frequency and High Voltage Center at the Institute of Microelectronics of the Chinese Academy of Sciences, has triumphantly unveiled a groundbreaking 112-Gb/s PAM-4 modulation retiming transceiver utilizing the ADC-DSP architecture. The team has innovatively introduced a novel jitter filtering clock scheme, leveraging injection-locked oscillators. This approach not only produces a synchronous recovery clock with minimal jitter but also drastically cuts down on the power consumption along the clock path. On the transmission side, they ingeniously designed an internal FFE (Feedforward Equalizer), a feedforward output driver, and a timing-optimized combiner, collectively contributing to a notable reduction in output jitter. At the receiving end, the team seamlessly integrated source degradation and resonant peak technology to create a continuous linear time equalizer. Additionally, they employed low-power, high-resolution digital equalization technology, significantly enhancing compensation accuracy and minimizing the bit error rate.