AI computing power chips are transitioning towards multi-chiplet architectures and three-dimensional stacking, resulting in a closer integration between chip design and advanced packaging processes. Consequently, ensuring seamless coordination among the toolchain, processes, and design to create a comprehensive solution that chip companies can leverage has emerged as a critical challenge for the 3D IC industry. Zhao Yi, the founder of Silicon Core Technology, emphasized the necessity of achieving coupling across all stages of the design process and fostering collaboration across all industrial sectors. The design process necessitates deep integration from architecture planning to testing and verification, while the industrial sectors require closed-loop cooperation among chip design, 3D IC EDA tools, and advanced packaging processes. Silicon Core Technology has already introduced a toolchain that encompasses the entire backend design process for 2.5D/3D stacked chips and is progressing with TCAD technology integration alongside Allchip Technologies to facilitate industrial collaboration. The Greater Bay Area 3D IC Advanced Packaging Innovation Center will concentrate on fostering synergy among advanced packaging, chip design, and 3D IC EDA tools, driving forward the development of an advanced packaging process library, a stacked chip design and development platform, and a 2.5D/3D EDA application promotion center.