Intel's Chief Technology Officer Pushkar Ranade pointed out in a podcast that even with ample funding, it is difficult to expand the global output of cutting-edge wafers by tenfold, with a more realistic growth ceiling of about two times. This bottleneck stems from the collaborative expansion capabilities of the entire semiconductor supply chain, rather than a single link. Currently, AI computing power is growing rapidly, but the scale of key equipment, cleanrooms, and wafer fabs required for manufacturing advanced chips is becoming a limiting factor for production capacity. ASML produces fewer than 100 EUV lithography machines annually and will find it difficult to significantly expand production by the end of this decade, with related equipment delivery cycles of about 18 months. New wafer fabs also often fail to automatically increase production due to insufficient equipment supply. Only by synchronously expanding production across all links in the supply chain, including lithography machines, key components, and materials, can the output of advanced wafers be significantly increased.