On August 31, 2026, the SPMP (Privileged State Physical Memory Protection) instruction set standard, developed under the leadership of the Institute of Parallel and Distributed Systems (IPADS) at Shanghai Jiao Tong University, successfully navigated the review process conducted by the Board of Directors of the RISC-V International Foundation. The standard was subsequently approved for incorporation into the RISC-V Instruction Set Architecture (ISA) standard. This achievement represents the inaugural instance where an ISA standard feature has been conceived and fully guided by a Chinese team from inception, since the inception of the RISC-V International Foundation in 2015. The SPMP standard accomplishes memory isolation via registers, thereby minimizing hardware overhead and power consumption. It lays a solid security foundation for devices that are sensitive to power consumption and area constraints, such as AI chips, automotive chips, and smart terminals. Prior to this, the core standards of RISC-V were predominantly shaped by overseas entities. The integration of SPMP into the RISC-V standard marks a significant milestone, amplifying China's influence and presence in the realm of international core chip standards.