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Following the development of FinFET and Gate-All-Around (GAA) nanosheet technologies, Complementary Field-Effect Transistor (CFET) technology has emerged as a pivotal architecture. It achieves this by vertically stacking N-type Field-Effect Transistors (N-FETs) and P-type Field-Effect Transistors (P-FETs), offering a significant boost in logic density, a reduction in interconnection lengths, and a decrease in cell area. The International Roadmap for Devices and Systems (IRDS) has designated CFET as a vital device form for technology nodes below 2nm and forecasts its practical implementation around 2032. At recent international semiconductor technology conferences, such as the International Electron Devices Meeting (IEDM) and the Symposia on VLSI Technology and Circuits (VLSI), CFET technology has taken center stage as a key topic of discussion.
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